b4e8c8dd84
This is a trivial 4xx plaform that uses the new simple bsp from Josh and is handy to use in simulators such as ISS or even Mambo who don't properly implement most of the actual devices in the SoC but really only the core. Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
156 lines
3.8 KiB
Plaintext
156 lines
3.8 KiB
Plaintext
/*
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* Device Tree Source for IBM Embedded PPC 476 Platform
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*
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* Copyright 2010 Torez Smith, IBM Corporation.
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*
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* Based on earlier code:
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* Copyright (c) 2006, 2007 IBM Corp.
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* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/memreserve/ 0x01f00000 0x00100000;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "ibm,iss-4xx";
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compatible = "ibm,iss-4xx";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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serial0 = &UART0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,4xx"; // real CPU changed in sim
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reg = <0>;
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clock-frequency = <100000000>; // 100Mhz :-)
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timebase-frequency = <100000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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status = "ok";
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};
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cpu@1 {
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device_type = "cpu";
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model = "PowerPC,4xx"; // real CPU changed in sim
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reg = <1>;
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clock-frequency = <100000000>; // 100Mhz :-)
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timebase-frequency = <100000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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status = "disabled";
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enable-method = "spin-table";
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cpu-release-addr = <0 0x01f00100>;
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};
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cpu@2 {
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device_type = "cpu";
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model = "PowerPC,4xx"; // real CPU changed in sim
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reg = <2>;
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clock-frequency = <100000000>; // 100Mhz :-)
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timebase-frequency = <100000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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status = "disabled";
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enable-method = "spin-table";
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cpu-release-addr = <0 0x01f00200>;
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};
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cpu@3 {
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device_type = "cpu";
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model = "PowerPC,4xx"; // real CPU changed in sim
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reg = <3>;
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clock-frequency = <100000000>; // 100Mhz :-)
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timebase-frequency = <100000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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status = "disabled";
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enable-method = "spin-table";
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cpu-release-addr = <0 0x01f00300>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
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};
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MPIC: interrupt-controller {
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compatible = "chrp,open-pic";
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interrupt-controller;
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dcr-reg = <0xffc00000 0x00030000>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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plb {
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compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; // Filled in by zImage
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POB0: opb {
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compatible = "ibm,opb-4xx", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Wish there was a nicer way of specifying a full 32-bit
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range */
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ranges = <0x00000000 0x00000001 0x00000000 0x80000000
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0x80000000 0x00000001 0x80000000 0x80000000>;
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clock-frequency = <0>; // Filled in by zImage
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UART0: serial@40000200 {
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0x40000200 0x00000008>;
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virtual-reg = <0xe0000200>;
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clock-frequency = <11059200>;
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current-speed = <115200>;
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interrupt-parent = <&MPIC>;
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interrupts = <0x0 0x2>;
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};
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};
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};
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nvrtc {
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compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
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reg = <0 0xEF703000 0x2000>;
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};
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iss-block {
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compatible = "ibm,iss-sim-block-device";
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reg = <0 0xEF701000 0x1000>;
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};
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chosen {
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linux,stdout-path = "/plb/opb/serial@40000200";
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};
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};
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