273 lines
7.9 KiB
C
273 lines
7.9 KiB
C
/*
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* Copyright (c) 2016-2017 Hisilicon Limited.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _HNS_ROCE_HW_V2_H
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#define _HNS_ROCE_HW_V2_H
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#include <linux/bitops.h>
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#define HNS_ROCE_VF_QPC_BT_NUM 256
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#define HNS_ROCE_VF_SRQC_BT_NUM 64
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#define HNS_ROCE_VF_CQC_BT_NUM 64
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#define HNS_ROCE_VF_MPT_BT_NUM 64
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#define HNS_ROCE_VF_EQC_NUM 64
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#define HNS_ROCE_VF_SMAC_NUM 32
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#define HNS_ROCE_VF_SGID_NUM 32
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#define HNS_ROCE_VF_SL_NUM 8
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#define HNS_ROCE_V2_MAX_QP_NUM 0x2000
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#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
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#define HNS_ROCE_V2_MAX_CQ_NUM 0x8000
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#define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
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#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
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#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
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#define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
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#define HNS_ROCE_V2_UAR_NUM 256
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#define HNS_ROCE_V2_PHY_UAR_NUM 1
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#define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000
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#define HNS_ROCE_V2_MAX_MTT_SEGS 0x100000
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#define HNS_ROCE_V2_MAX_CQE_SEGS 0x10000
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#define HNS_ROCE_V2_MAX_PD_NUM 0x400000
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#define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
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#define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
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#define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
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#define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
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#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
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#define HNS_ROCE_V2_QPC_ENTRY_SZ 256
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#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
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#define HNS_ROCE_V2_CQC_ENTRY_SZ 64
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#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
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#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
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#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
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#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
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#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
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#define HNS_ROCE_CMQ_TX_TIMEOUT 200
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#define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
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#define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
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#define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
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#define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
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#define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
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#define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
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#define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
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#define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
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#define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
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#define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
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#define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
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#define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
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#define HNS_ROCE_CMQ_DESC_NUM_S 3
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#define HNS_ROCE_CMQ_EN_B 16
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#define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B)
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/* CMQ command */
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enum hns_roce_opcode_type {
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HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
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HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
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HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
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HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
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HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
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HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
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};
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enum {
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TYPE_CRQ,
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TYPE_CSQ,
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};
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enum hns_roce_cmd_return_status {
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CMD_EXEC_SUCCESS = 0,
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CMD_NO_AUTH = 1,
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CMD_NOT_EXEC = 2,
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CMD_QUEUE_FULL = 3,
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};
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struct hns_roce_query_version {
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__le16 rocee_vendor_id;
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__le16 rocee_hw_version;
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__le32 rsv[5];
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};
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struct hns_roce_cfg_global_param {
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__le32 time_cfg_udp_port;
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__le32 rsv[5];
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};
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#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
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#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
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#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
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#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
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struct hns_roce_pf_res {
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__le32 rsv;
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__le32 qpc_bt_idx_num;
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__le32 srqc_bt_idx_num;
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__le32 cqc_bt_idx_num;
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__le32 mpt_bt_idx_num;
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__le32 eqc_bt_idx_num;
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};
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#define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
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#define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
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#define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
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#define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
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#define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
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#define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
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#define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
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#define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
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#define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
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#define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
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#define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
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#define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
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#define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
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#define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
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#define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
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#define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
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#define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
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#define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
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#define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
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#define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
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struct hns_roce_vf_res_a {
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u32 vf_id;
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u32 vf_qpc_bt_idx_num;
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u32 vf_srqc_bt_idx_num;
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u32 vf_cqc_bt_idx_num;
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u32 vf_mpt_bt_idx_num;
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u32 vf_eqc_bt_idx_num;
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};
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#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
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#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
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#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
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#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
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#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
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#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
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#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
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#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
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#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
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#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
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#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
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#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
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#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
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#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
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#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
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#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
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#define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
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#define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
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#define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
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#define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
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struct hns_roce_vf_res_b {
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u32 rsv0;
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u32 vf_smac_idx_num;
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u32 vf_sgid_idx_num;
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u32 vf_qid_idx_sl_num;
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u32 rsv[2];
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};
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#define VF_RES_B_DATA_0_VF_ID_S 0
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#define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
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#define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
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#define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
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#define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
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#define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
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#define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
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#define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
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#define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
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#define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
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#define VF_RES_B_DATA_3_VF_QID_IDX_S 0
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#define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
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#define VF_RES_B_DATA_3_VF_SL_NUM_S 16
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#define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
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struct hns_roce_cmq_desc {
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u16 opcode;
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u16 flag;
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u16 retval;
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u16 rsv;
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u32 data[6];
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};
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struct hns_roce_v2_cmq_ring {
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dma_addr_t desc_dma_addr;
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struct hns_roce_cmq_desc *desc;
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u32 head;
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u32 tail;
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u16 buf_size;
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u16 desc_num;
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int next_to_use;
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int next_to_clean;
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u8 flag;
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spinlock_t lock; /* command queue lock */
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};
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struct hns_roce_v2_cmq {
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struct hns_roce_v2_cmq_ring csq;
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struct hns_roce_v2_cmq_ring crq;
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u16 tx_timeout;
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u16 last_status;
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};
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struct hns_roce_v2_priv {
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struct hns_roce_v2_cmq cmq;
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};
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#endif
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