Greentime Hu abb90a24ea nds32: To fix a cache inconsistency issue by setting correct cacheability of NTC ... The nds32 architecture will use physical memory when interrupt or exception comes and it will use the setting of NTC0-4. The original implementation didn't consider the DRAM start address may start from 1GB, 2GB or 3GB to cause this issue. It will write the data to DRAM if it is running in physical address however kernel will read the data with virtaul address through data cache. In this case, the data of DRAM is latest. This fix will set the correct cacheability to let kernel write/read the latest data in cache instead of DRAM. Signed-off-by: Greentime Hu <greentime@andestech.com>		2018-05-23 13:26:22 +08:00
..
asm	nds32: To fix a cache inconsistency issue by setting correct cacheability of NTC	2018-05-23 13:26:22 +08:00
uapi/asm	nds32: Build infrastructure	2018-02-22 10:44:35 +08:00