![Stephen Rothwell](/assets/img/avatar_default.png)
Today's linux-next build (powerpc allyesconfig) failed like this:
drivers/char/agp/uninorth-agp.c:541: error: unknown field 'agp_destroy_paged' specified in initializer
Caused by commit 5f310b6378
("agp: enable optimized agp_alloc_pages methods"). A simple typo ...
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
710 lines
18 KiB
C
710 lines
18 KiB
C
/*
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* UniNorth AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/pagemap.h>
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#include <linux/agp_backend.h>
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#include <linux/delay.h>
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#include <asm/uninorth.h>
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#include <asm/pci-bridge.h>
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#include <asm/prom.h>
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#include <asm/pmac_feature.h>
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#include "agp.h"
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/*
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* NOTES for uninorth3 (G5 AGP) supports :
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*
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* There maybe also possibility to have bigger cache line size for
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* agp (see pmac_pci.c and look for cache line). Need to be investigated
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* by someone.
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*
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* PAGE size are hardcoded but this may change, see asm/page.h.
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*
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* Jerome Glisse <j.glisse@gmail.com>
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*/
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static int uninorth_rev;
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static int is_u3;
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static char __devinitdata *aperture = NULL;
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static int uninorth_fetch_size(void)
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{
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int i, size = 0;
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struct aper_size_info_32 *values =
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A_SIZE_32(agp_bridge->driver->aperture_sizes);
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if (aperture) {
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char *save = aperture;
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size = memparse(aperture, &aperture) >> 20;
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aperture = save;
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
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if (size == values[i].size)
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break;
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if (i == agp_bridge->driver->num_aperture_sizes) {
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dev_err(&agp_bridge->dev->dev, "invalid aperture size, "
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"using default\n");
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size = 0;
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aperture = NULL;
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}
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}
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if (!size) {
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
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if (values[i].size == 32)
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break;
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}
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *)(values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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static void uninorth_tlbflush(struct agp_memory *mem)
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{
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u32 ctrl = UNI_N_CFG_GART_ENABLE;
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if (is_u3)
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ctrl |= U3_N_CFG_GART_PERFRD;
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
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ctrl | UNI_N_CFG_GART_INVAL);
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
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if (uninorth_rev <= 0x30) {
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
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ctrl | UNI_N_CFG_GART_2xRESET);
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
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ctrl);
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}
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}
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static void uninorth_cleanup(void)
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{
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u32 tmp;
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pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp);
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if (!(tmp & UNI_N_CFG_GART_ENABLE))
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return;
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tmp |= UNI_N_CFG_GART_INVAL;
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp);
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0);
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if (uninorth_rev <= 0x30) {
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
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UNI_N_CFG_GART_2xRESET);
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
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0);
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}
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}
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static int uninorth_configure(void)
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{
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struct aper_size_info_32 *current_size;
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current_size = A_SIZE_32(agp_bridge->current_size);
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dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n",
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current_size->size_value);
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/* aperture size and gatt addr */
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pci_write_config_dword(agp_bridge->dev,
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UNI_N_CFG_GART_BASE,
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(agp_bridge->gatt_bus_addr & 0xfffff000)
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| current_size->size_value);
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/* HACK ALERT
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* UniNorth seem to be buggy enough not to handle properly when
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* the AGP aperture isn't mapped at bus physical address 0
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*/
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agp_bridge->gart_bus_addr = 0;
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#ifdef CONFIG_PPC64
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/* Assume U3 or later on PPC64 systems */
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/* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */
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pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE,
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(agp_bridge->gatt_bus_addr >> 32) & 0xf);
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#else
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pci_write_config_dword(agp_bridge->dev,
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UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr);
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#endif
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if (is_u3) {
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pci_write_config_dword(agp_bridge->dev,
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UNI_N_CFG_GART_DUMMY_PAGE,
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agp_bridge->scratch_page_real >> 12);
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}
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return 0;
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}
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static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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int i, j, num_entries;
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void *temp;
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temp = agp_bridge->current_size;
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num_entries = A_SIZE_32(temp)->num_entries;
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if (type != 0 || mem->type != 0)
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/* We know nothing of memory types */
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return -EINVAL;
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if ((pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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j = pg_start;
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while (j < (pg_start + mem->page_count)) {
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if (agp_bridge->gatt_table[j])
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return -EBUSY;
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j++;
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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agp_bridge->gatt_table[j] =
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cpu_to_le32((mem->memory[i] & 0xFFFFF000UL) | 0x1UL);
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flush_dcache_range((unsigned long)__va(mem->memory[i]),
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(unsigned long)__va(mem->memory[i])+0x1000);
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}
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(void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
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mb();
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flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
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(unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]);
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uninorth_tlbflush(mem);
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return 0;
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}
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static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i, num_entries;
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void *temp;
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u32 *gp;
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temp = agp_bridge->current_size;
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num_entries = A_SIZE_32(temp)->num_entries;
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if (type != 0 || mem->type != 0)
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/* We know nothing of memory types */
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return -EINVAL;
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if ((pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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gp = (u32 *) &agp_bridge->gatt_table[pg_start];
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for (i = 0; i < mem->page_count; ++i) {
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if (gp[i]) {
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dev_info(&agp_bridge->dev->dev,
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"u3_insert_memory: entry 0x%x occupied (%x)\n",
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i, gp[i]);
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return -EBUSY;
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}
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}
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for (i = 0; i < mem->page_count; i++) {
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gp[i] = (mem->memory[i] >> PAGE_SHIFT) | 0x80000000UL;
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flush_dcache_range((unsigned long)__va(mem->memory[i]),
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(unsigned long)__va(mem->memory[i])+0x1000);
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}
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mb();
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flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]);
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uninorth_tlbflush(mem);
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return 0;
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}
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int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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size_t i;
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u32 *gp;
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if (type != 0 || mem->type != 0)
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/* We know nothing of memory types */
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return -EINVAL;
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gp = (u32 *) &agp_bridge->gatt_table[pg_start];
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for (i = 0; i < mem->page_count; ++i)
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gp[i] = 0;
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mb();
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flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]);
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uninorth_tlbflush(mem);
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return 0;
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}
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static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
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{
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u32 command, scratch, status;
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int timeout;
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pci_read_config_dword(bridge->dev,
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bridge->capndx + PCI_AGP_STATUS,
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&status);
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command = agp_collect_device_status(bridge, mode, status);
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command |= PCI_AGP_COMMAND_AGP;
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if (uninorth_rev == 0x21) {
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/*
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* Darwin disable AGP 4x on this revision, thus we
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* may assume it's broken. This is an AGP2 controller.
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*/
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command &= ~AGPSTAT2_4X;
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}
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if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
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/*
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* We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
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* 2.2 and 2.3, Darwin do so.
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*/
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if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7)
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command = (command & ~AGPSTAT_RQ_DEPTH)
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| (7 << AGPSTAT_RQ_DEPTH_SHIFT);
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}
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uninorth_tlbflush(NULL);
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timeout = 0;
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do {
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pci_write_config_dword(bridge->dev,
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bridge->capndx + PCI_AGP_COMMAND,
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command);
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pci_read_config_dword(bridge->dev,
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bridge->capndx + PCI_AGP_COMMAND,
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&scratch);
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} while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000);
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if ((scratch & PCI_AGP_COMMAND_AGP) == 0)
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dev_err(&bridge->dev->dev, "can't write UniNorth AGP "
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"command register\n");
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if (uninorth_rev >= 0x30) {
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/* This is an AGP V3 */
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agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
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} else {
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/* AGP V2 */
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agp_device_command(command, false);
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}
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uninorth_tlbflush(NULL);
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}
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#ifdef CONFIG_PM
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/*
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* These Power Management routines are _not_ called by the normal PCI PM layer,
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* but directly by the video driver through function pointers in the device
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* tree.
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*/
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static int agp_uninorth_suspend(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge;
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u32 cmd;
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u8 agp;
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struct pci_dev *device = NULL;
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bridge = agp_find_bridge(pdev);
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if (bridge == NULL)
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return -ENODEV;
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/* Only one suspend supported */
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if (bridge->dev_private_data)
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return 0;
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/* turn off AGP on the video chip, if it was enabled */
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for_each_pci_dev(device) {
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/* Don't touch the bridge yet, device first */
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if (device == pdev)
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continue;
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/* Only deal with devices on the same bus here, no Mac has a P2P
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* bridge on the AGP port, and mucking around the entire PCI
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* tree is source of problems on some machines because of a bug
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* in some versions of pci_find_capability() when hitting a dead
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* device
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*/
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if (device->bus != pdev->bus)
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continue;
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agp = pci_find_capability(device, PCI_CAP_ID_AGP);
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if (!agp)
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continue;
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pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd);
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if (!(cmd & PCI_AGP_COMMAND_AGP))
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continue;
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dev_info(&pdev->dev, "disabling AGP on device %s\n",
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pci_name(device));
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cmd &= ~PCI_AGP_COMMAND_AGP;
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pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd);
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}
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/* turn off AGP on the bridge */
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agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
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bridge->dev_private_data = (void *)(long)cmd;
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if (cmd & PCI_AGP_COMMAND_AGP) {
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dev_info(&pdev->dev, "disabling AGP on bridge\n");
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cmd &= ~PCI_AGP_COMMAND_AGP;
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pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd);
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}
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/* turn off the GART */
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uninorth_cleanup();
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return 0;
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}
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static int agp_uninorth_resume(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge;
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u32 command;
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bridge = agp_find_bridge(pdev);
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if (bridge == NULL)
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return -ENODEV;
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command = (long)bridge->dev_private_data;
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bridge->dev_private_data = NULL;
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if (!(command & PCI_AGP_COMMAND_AGP))
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return 0;
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uninorth_agp_enable(bridge, command);
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return 0;
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}
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#endif /* CONFIG_PM */
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static int uninorth_create_gatt_table(struct agp_bridge_data *bridge)
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{
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char *table;
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char *table_end;
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int size;
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int page_order;
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int num_entries;
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int i;
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void *temp;
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struct page *page;
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/* We can't handle 2 level gatt's */
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if (bridge->driver->size_type == LVL2_APER_SIZE)
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return -EINVAL;
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table = NULL;
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i = bridge->aperture_size_idx;
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temp = bridge->current_size;
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size = page_order = num_entries = 0;
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do {
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size = A_SIZE_32(temp)->size;
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page_order = A_SIZE_32(temp)->page_order;
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num_entries = A_SIZE_32(temp)->num_entries;
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table = (char *) __get_free_pages(GFP_KERNEL, page_order);
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if (table == NULL) {
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i++;
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bridge->current_size = A_IDX32(bridge);
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} else {
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bridge->aperture_size_idx = i;
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}
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} while (!table && (i < bridge->driver->num_aperture_sizes));
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if (table == NULL)
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return -ENOMEM;
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table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
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for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
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SetPageReserved(page);
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bridge->gatt_table_real = (u32 *) table;
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bridge->gatt_table = (u32 *)table;
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bridge->gatt_bus_addr = virt_to_gart(table);
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for (i = 0; i < num_entries; i++)
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bridge->gatt_table[i] = 0;
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flush_dcache_range((unsigned long)table, (unsigned long)table_end);
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return 0;
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}
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static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
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{
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int page_order;
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char *table, *table_end;
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void *temp;
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struct page *page;
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temp = bridge->current_size;
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page_order = A_SIZE_32(temp)->page_order;
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/* Do not worry about freeing memory, because if this is
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* called, then all agp memory is deallocated and removed
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* from the table.
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*/
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table = (char *) bridge->gatt_table_real;
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table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
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for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
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ClearPageReserved(page);
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free_pages((unsigned long) bridge->gatt_table_real, page_order);
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return 0;
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}
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void null_cache_flush(void)
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{
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mb();
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}
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/* Setup function */
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static const struct aper_size_info_32 uninorth_sizes[7] =
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{
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#if 0 /* Not sure uninorth supports that high aperture sizes */
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{256, 65536, 6, 64},
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{128, 32768, 5, 32},
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{64, 16384, 4, 16},
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#endif
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{32, 8192, 3, 8},
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{16, 4096, 2, 4},
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{8, 2048, 1, 2},
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{4, 1024, 0, 1}
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};
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/*
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* Not sure that u3 supports that high aperture sizes but it
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* would strange if it did not :)
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*/
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static const struct aper_size_info_32 u3_sizes[8] =
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{
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{512, 131072, 7, 128},
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{256, 65536, 6, 64},
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{128, 32768, 5, 32},
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{64, 16384, 4, 16},
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{32, 8192, 3, 8},
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{16, 4096, 2, 4},
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{8, 2048, 1, 2},
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{4, 1024, 0, 1}
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};
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const struct agp_bridge_driver uninorth_agp_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = (void *)uninorth_sizes,
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|
.size_type = U32_APER_SIZE,
|
|
.num_aperture_sizes = 4,
|
|
.configure = uninorth_configure,
|
|
.fetch_size = uninorth_fetch_size,
|
|
.cleanup = uninorth_cleanup,
|
|
.tlb_flush = uninorth_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = NULL,
|
|
.cache_flush = null_cache_flush,
|
|
.agp_enable = uninorth_agp_enable,
|
|
.create_gatt_table = uninorth_create_gatt_table,
|
|
.free_gatt_table = uninorth_free_gatt_table,
|
|
.insert_memory = uninorth_insert_memory,
|
|
.remove_memory = agp_generic_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
.cant_use_aperture = true,
|
|
};
|
|
|
|
const struct agp_bridge_driver u3_agp_driver = {
|
|
.owner = THIS_MODULE,
|
|
.aperture_sizes = (void *)u3_sizes,
|
|
.size_type = U32_APER_SIZE,
|
|
.num_aperture_sizes = 8,
|
|
.configure = uninorth_configure,
|
|
.fetch_size = uninorth_fetch_size,
|
|
.cleanup = uninorth_cleanup,
|
|
.tlb_flush = uninorth_tlbflush,
|
|
.mask_memory = agp_generic_mask_memory,
|
|
.masks = NULL,
|
|
.cache_flush = null_cache_flush,
|
|
.agp_enable = uninorth_agp_enable,
|
|
.create_gatt_table = uninorth_create_gatt_table,
|
|
.free_gatt_table = uninorth_free_gatt_table,
|
|
.insert_memory = u3_insert_memory,
|
|
.remove_memory = u3_remove_memory,
|
|
.alloc_by_type = agp_generic_alloc_by_type,
|
|
.free_by_type = agp_generic_free_by_type,
|
|
.agp_alloc_page = agp_generic_alloc_page,
|
|
.agp_alloc_pages = agp_generic_alloc_pages,
|
|
.agp_destroy_page = agp_generic_destroy_page,
|
|
.agp_destroy_pages = agp_generic_destroy_pages,
|
|
.agp_type_to_mask_type = agp_generic_type_to_mask_type,
|
|
.cant_use_aperture = true,
|
|
.needs_scratch_page = true,
|
|
};
|
|
|
|
static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
|
|
.chipset_name = "UniNorth",
|
|
},
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P,
|
|
.chipset_name = "UniNorth/Pangea",
|
|
},
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15,
|
|
.chipset_name = "UniNorth 1.5",
|
|
},
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
|
|
.chipset_name = "UniNorth 2",
|
|
},
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
|
|
.chipset_name = "U3",
|
|
},
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_U3L_AGP,
|
|
.chipset_name = "U3L",
|
|
},
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_U3H_AGP,
|
|
.chipset_name = "U3H",
|
|
},
|
|
{
|
|
.device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP,
|
|
.chipset_name = "UniNorth/Intrepid2",
|
|
},
|
|
};
|
|
|
|
static int __devinit agp_uninorth_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct agp_device_ids *devs = uninorth_agp_device_ids;
|
|
struct agp_bridge_data *bridge;
|
|
struct device_node *uninorth_node;
|
|
u8 cap_ptr;
|
|
int j;
|
|
|
|
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
|
|
if (cap_ptr == 0)
|
|
return -ENODEV;
|
|
|
|
/* probe for known chipsets */
|
|
for (j = 0; devs[j].chipset_name != NULL; ++j) {
|
|
if (pdev->device == devs[j].device_id) {
|
|
dev_info(&pdev->dev, "Apple %s chipset\n",
|
|
devs[j].chipset_name);
|
|
goto found;
|
|
}
|
|
}
|
|
|
|
dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n",
|
|
pdev->vendor, pdev->device);
|
|
return -ENODEV;
|
|
|
|
found:
|
|
/* Set revision to 0 if we could not read it. */
|
|
uninorth_rev = 0;
|
|
is_u3 = 0;
|
|
/* Locate core99 Uni-N */
|
|
uninorth_node = of_find_node_by_name(NULL, "uni-n");
|
|
/* Locate G5 u3 */
|
|
if (uninorth_node == NULL) {
|
|
is_u3 = 1;
|
|
uninorth_node = of_find_node_by_name(NULL, "u3");
|
|
}
|
|
if (uninorth_node) {
|
|
const int *revprop = of_get_property(uninorth_node,
|
|
"device-rev", NULL);
|
|
if (revprop != NULL)
|
|
uninorth_rev = *revprop & 0x3f;
|
|
of_node_put(uninorth_node);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
/* Inform platform of our suspend/resume caps */
|
|
pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume);
|
|
#endif
|
|
|
|
/* Allocate & setup our driver */
|
|
bridge = agp_alloc_bridge();
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
if (is_u3)
|
|
bridge->driver = &u3_agp_driver;
|
|
else
|
|
bridge->driver = &uninorth_agp_driver;
|
|
|
|
bridge->dev = pdev;
|
|
bridge->capndx = cap_ptr;
|
|
bridge->flags = AGP_ERRATA_FASTWRITES;
|
|
|
|
/* Fill in the mode register */
|
|
pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode);
|
|
|
|
pci_set_drvdata(pdev, bridge);
|
|
return agp_add_bridge(bridge);
|
|
}
|
|
|
|
static void __devexit agp_uninorth_remove(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
#ifdef CONFIG_PM
|
|
/* Inform platform of our suspend/resume caps */
|
|
pmac_register_agp_pm(pdev, NULL, NULL);
|
|
#endif
|
|
|
|
agp_remove_bridge(bridge);
|
|
agp_put_bridge(bridge);
|
|
}
|
|
|
|
static struct pci_device_id agp_uninorth_pci_table[] = {
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_APPLE,
|
|
.device = PCI_ANY_ID,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table);
|
|
|
|
static struct pci_driver agp_uninorth_pci_driver = {
|
|
.name = "agpgart-uninorth",
|
|
.id_table = agp_uninorth_pci_table,
|
|
.probe = agp_uninorth_probe,
|
|
.remove = agp_uninorth_remove,
|
|
};
|
|
|
|
static int __init agp_uninorth_init(void)
|
|
{
|
|
if (agp_off)
|
|
return -EINVAL;
|
|
return pci_register_driver(&agp_uninorth_pci_driver);
|
|
}
|
|
|
|
static void __exit agp_uninorth_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&agp_uninorth_pci_driver);
|
|
}
|
|
|
|
module_init(agp_uninorth_init);
|
|
module_exit(agp_uninorth_cleanup);
|
|
|
|
module_param(aperture, charp, 0);
|
|
MODULE_PARM_DESC(aperture,
|
|
"Aperture size, must be power of two between 4MB and an\n"
|
|
"\t\tupper limit specific to the UniNorth revision.\n"
|
|
"\t\tDefault: 32M");
|
|
|
|
MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras");
|
|
MODULE_LICENSE("GPL");
|