078a55fc82
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
152 lines
3.6 KiB
C
152 lines
3.6 KiB
C
/*
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* Count register synchronisation.
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*
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* All CPUs will have their count registers synchronised to the CPU0 next time
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* value. This can cause a small timewarp for CPU0. All other CPU's should
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* not have done anything significant (but they may have had interrupts
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* enabled briefly - prom_smp_finish() should not be responsible for enabling
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* interrupts...)
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*
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* FIXME: broken for SMTC
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irqflags.h>
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#include <linux/cpumask.h>
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#include <asm/r4k-timer.h>
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#include <linux/atomic.h>
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#include <asm/barrier.h>
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#include <asm/mipsregs.h>
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static atomic_t count_start_flag = ATOMIC_INIT(0);
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static atomic_t count_count_start = ATOMIC_INIT(0);
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static atomic_t count_count_stop = ATOMIC_INIT(0);
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static atomic_t count_reference = ATOMIC_INIT(0);
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#define COUNTON 100
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#define NR_LOOPS 5
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void synchronise_count_master(int cpu)
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{
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int i;
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unsigned long flags;
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unsigned int initcount;
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC needs to synchronise per VPE, not per CPU
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* ignore for now
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*/
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return;
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#endif
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printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
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local_irq_save(flags);
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/*
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* Notify the slaves that it's time to start
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*/
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atomic_set(&count_reference, read_c0_count());
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atomic_set(&count_start_flag, cpu);
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smp_wmb();
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/* Count will be initialised to current timer for all CPU's */
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initcount = read_c0_count();
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/*
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* We loop a few times to get a primed instruction cache,
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* then the last pass is more or less synchronised and
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* the master and slaves each set their cycle counters to a known
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* value all at once. This reduces the chance of having random offsets
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* between the processors, and guarantees that the maximum
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* delay between the cycle counters is never bigger than
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* the latency of information-passing (cachelines) between
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* two CPUs.
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*/
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for (i = 0; i < NR_LOOPS; i++) {
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/* slaves loop on '!= 2' */
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while (atomic_read(&count_count_start) != 1)
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mb();
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atomic_set(&count_count_stop, 0);
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smp_wmb();
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/* this lets the slaves write their count register */
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atomic_inc(&count_count_start);
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/*
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* Everyone initialises count in the last loop:
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*/
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if (i == NR_LOOPS-1)
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write_c0_count(initcount);
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/*
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* Wait for all slaves to leave the synchronization point:
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*/
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while (atomic_read(&count_count_stop) != 1)
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mb();
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atomic_set(&count_count_start, 0);
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smp_wmb();
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atomic_inc(&count_count_stop);
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}
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/* Arrange for an interrupt in a short while */
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write_c0_compare(read_c0_count() + COUNTON);
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atomic_set(&count_start_flag, 0);
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local_irq_restore(flags);
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/*
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* i386 code reported the skew here, but the
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* count registers were almost certainly out of sync
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* so no point in alarming people
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*/
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printk("done.\n");
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}
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void synchronise_count_slave(int cpu)
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{
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int i;
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unsigned int initcount;
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC needs to synchronise per VPE, not per CPU
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* ignore for now
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*/
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return;
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#endif
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/*
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* Not every cpu is online at the time this gets called,
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* so we first wait for the master to say everyone is ready
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*/
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while (atomic_read(&count_start_flag) != cpu)
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mb();
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/* Count will be initialised to next expire for all CPU's */
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initcount = atomic_read(&count_reference);
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for (i = 0; i < NR_LOOPS; i++) {
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atomic_inc(&count_count_start);
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while (atomic_read(&count_count_start) != 2)
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mb();
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/*
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* Everyone initialises count in the last loop:
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*/
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if (i == NR_LOOPS-1)
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write_c0_count(initcount);
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atomic_inc(&count_count_stop);
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while (atomic_read(&count_count_stop) != 2)
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mb();
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}
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/* Arrange for an interrupt in a short while */
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write_c0_compare(read_c0_count() + COUNTON);
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}
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#undef NR_LOOPS
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