50c8308538
Currently, the following instructions are translated: - CACHE (indexed) - CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations, but still much faster than a trap. - mfc0/mtc0: the virtual COP0 registers for the guest are implemented as 2-D array. [COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0. mfc0/mtc0 operations are transformed to load/stores. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
24 lines
666 B
C
24 lines
666 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS: commpage: mapped into get kernel space
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#ifndef __KVM_MIPS_COMMPAGE_H__
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#define __KVM_MIPS_COMMPAGE_H__
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struct kvm_mips_commpage {
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struct mips_coproc cop0; /* COP0 state is mapped into Guest kernel via commpage */
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};
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#define KVM_MIPS_COMM_EIDI_OFFSET 0x0
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extern void kvm_mips_commpage_init(struct kvm_vcpu *vcpu);
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#endif /* __KVM_MIPS_COMMPAGE_H__ */
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