9952f6918d
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
61 lines
1.2 KiB
C
61 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __SOC_TEGRA_FUSE_H__
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#define __SOC_TEGRA_FUSE_H__
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#define TEGRA20 0x20
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#define TEGRA30 0x30
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#define TEGRA114 0x35
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#define TEGRA124 0x40
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#define TEGRA132 0x13
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#define TEGRA210 0x21
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#define TEGRA_FUSE_SKU_CALIB_0 0xf0
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#define TEGRA30_FUSE_SATA_CALIB 0x124
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#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
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#ifndef __ASSEMBLY__
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u32 tegra_read_chipid(void);
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u8 tegra_get_chip_id(void);
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enum tegra_revision {
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TEGRA_REVISION_UNKNOWN = 0,
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TEGRA_REVISION_A01,
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TEGRA_REVISION_A02,
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TEGRA_REVISION_A03,
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TEGRA_REVISION_A03p,
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TEGRA_REVISION_A04,
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TEGRA_REVISION_MAX,
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};
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struct tegra_sku_info {
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int sku_id;
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int cpu_process_id;
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int cpu_speedo_id;
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int cpu_speedo_value;
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int cpu_iddq_value;
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int soc_process_id;
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int soc_speedo_id;
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int soc_speedo_value;
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int gpu_process_id;
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int gpu_speedo_id;
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int gpu_speedo_value;
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enum tegra_revision revision;
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};
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u32 tegra_read_straps(void);
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u32 tegra_read_ram_code(void);
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int tegra_fuse_readl(unsigned long offset, u32 *value);
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extern struct tegra_sku_info tegra_sku_info;
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struct device *tegra_soc_device_register(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __SOC_TEGRA_FUSE_H__ */
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