612a9aab56
Pull drm merge (part 1) from Dave Airlie:
"So first of all my tree and uapi stuff has a conflict mess, its my
fault as the nouveau stuff didn't hit -next as were trying to rebase
regressions out of it before we merged.
Highlights:
- SH mobile modesetting driver and associated helpers
- some DRM core documentation
- i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write
combined pte writing, ilk rc6 support,
- nouveau: major driver rework into a hw core driver, makes features
like SLI a lot saner to implement,
- psb: add eDP/DP support for Cedarview
- radeon: 2 layer page tables, async VM pte updates, better PLL
selection for > 2 screens, better ACPI interactions
The rest is general grab bag of fixes.
So why part 1? well I have the exynos pull req which came in a bit
late but was waiting for me to do something they shouldn't have and it
looks fairly safe, and David Howells has some more header cleanups
he'd like me to pull, that seem like a good idea, but I'd like to get
this merge out of the way so -next dosen't get blocked."
Tons of conflicts mostly due to silly include line changes, but mostly
mindless. A few other small semantic conflicts too, noted from Dave's
pre-merged branch.
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits)
drm/nv98/crypt: fix fuc build with latest envyas
drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering
drm/nv41/vm: fix and enable use of "real" pciegart
drm/nv44/vm: fix and enable use of "real" pciegart
drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie
drm/nouveau: store supported dma mask in vmmgr
drm/nvc0/ibus: initial implementation of subdev
drm/nouveau/therm: add support for fan-control modes
drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules
drm/nouveau/therm: calculate the pwm divisor on nv50+
drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster
drm/nouveau/therm: move thermal-related functions to the therm subdev
drm/nouveau/bios: parse the pwm divisor from the perf table
drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices
drm/nouveau/therm: rework thermal table parsing
drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table
drm/nouveau: fix pm initialization order
drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it
drm/nouveau: log channel debug/error messages from client object rather than drm client
drm/nouveau: have drm debugging macros build on top of core macros
...
586 lines
18 KiB
C
586 lines
18 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Christian König.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "r600d.h"
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#include "atom.h"
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/*
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* HDMI color format
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*/
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enum r600_hdmi_color_format {
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RGB = 0,
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YCC_422 = 1,
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YCC_444 = 2
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};
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/*
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* IEC60958 status bits
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*/
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enum r600_hdmi_iec_status_bits {
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AUDIO_STATUS_DIG_ENABLE = 0x01,
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AUDIO_STATUS_V = 0x02,
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AUDIO_STATUS_VCFG = 0x04,
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AUDIO_STATUS_EMPHASIS = 0x08,
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AUDIO_STATUS_COPYRIGHT = 0x10,
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AUDIO_STATUS_NONAUDIO = 0x20,
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AUDIO_STATUS_PROFESSIONAL = 0x40,
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AUDIO_STATUS_LEVEL = 0x80
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};
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static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
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/* 32kHz 44.1kHz 48kHz */
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/* Clock N CTS N CTS N CTS */
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{ 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
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{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
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{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
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{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
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{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
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{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
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{ 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
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{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
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{ 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
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{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
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{ 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
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};
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/*
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* calculate CTS value if it's not found in the table
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*/
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static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
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{
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if (*CTS == 0)
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*CTS = clock * N / (128 * freq) * 1000;
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DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
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N, *CTS, freq);
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}
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struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
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{
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struct radeon_hdmi_acr res;
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u8 i;
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for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
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r600_hdmi_predefined_acr[i].clock != 0; i++)
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;
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res = r600_hdmi_predefined_acr[i];
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/* In case some CTS are missing */
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r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
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r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
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r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
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return res;
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}
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/*
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* update the N and CTS parameters for a given pixel clock rate
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*/
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static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
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WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
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WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
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WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
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WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
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WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
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}
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/*
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* calculate the crc for a given info frame
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*/
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static void r600_hdmi_infoframe_checksum(uint8_t packetType,
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uint8_t versionNumber,
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uint8_t length,
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uint8_t *frame)
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{
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int i;
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frame[0] = packetType + versionNumber + length;
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for (i = 1; i <= length; i++)
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frame[0] += frame[i];
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frame[0] = 0x100 - frame[0];
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}
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/*
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* build a HDMI Video Info Frame
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*/
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static void r600_hdmi_videoinfoframe(
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struct drm_encoder *encoder,
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enum r600_hdmi_color_format color_format,
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int active_information_present,
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uint8_t active_format_aspect_ratio,
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uint8_t scan_information,
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uint8_t colorimetry,
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uint8_t ex_colorimetry,
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uint8_t quantization,
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int ITC,
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uint8_t picture_aspect_ratio,
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uint8_t video_format_identification,
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uint8_t pixel_repetition,
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uint8_t non_uniform_picture_scaling,
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uint8_t bar_info_data_valid,
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uint16_t top_bar,
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uint16_t bottom_bar,
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uint16_t left_bar,
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uint16_t right_bar
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)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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uint8_t frame[14];
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frame[0x0] = 0;
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frame[0x1] =
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(scan_information & 0x3) |
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((bar_info_data_valid & 0x3) << 2) |
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((active_information_present & 0x1) << 4) |
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((color_format & 0x3) << 5);
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frame[0x2] =
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(active_format_aspect_ratio & 0xF) |
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((picture_aspect_ratio & 0x3) << 4) |
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((colorimetry & 0x3) << 6);
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frame[0x3] =
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(non_uniform_picture_scaling & 0x3) |
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((quantization & 0x3) << 2) |
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((ex_colorimetry & 0x7) << 4) |
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((ITC & 0x1) << 7);
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frame[0x4] = (video_format_identification & 0x7F);
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frame[0x5] = (pixel_repetition & 0xF);
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frame[0x6] = (top_bar & 0xFF);
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frame[0x7] = (top_bar >> 8);
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frame[0x8] = (bottom_bar & 0xFF);
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frame[0x9] = (bottom_bar >> 8);
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frame[0xA] = (left_bar & 0xFF);
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frame[0xB] = (left_bar >> 8);
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frame[0xC] = (right_bar & 0xFF);
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frame[0xD] = (right_bar >> 8);
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r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
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/* Our header values (type, version, length) should be alright, Intel
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* is using the same. Checksum function also seems to be OK, it works
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* fine for audio infoframe. However calculated value is always lower
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* by 2 in comparison to fglrx. It breaks displaying anything in case
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* of TVs that strictly check the checksum. Hack it manually here to
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* workaround this issue. */
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frame[0x0] += 2;
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WREG32(HDMI0_AVI_INFO0 + offset,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(HDMI0_AVI_INFO1 + offset,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
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WREG32(HDMI0_AVI_INFO2 + offset,
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frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
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WREG32(HDMI0_AVI_INFO3 + offset,
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frame[0xC] | (frame[0xD] << 8));
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}
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/*
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* build a Audio Info Frame
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*/
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static void r600_hdmi_audioinfoframe(
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struct drm_encoder *encoder,
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uint8_t channel_count,
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uint8_t coding_type,
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uint8_t sample_size,
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uint8_t sample_frequency,
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uint8_t format,
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uint8_t channel_allocation,
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uint8_t level_shift,
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int downmix_inhibit
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)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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uint8_t frame[11];
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frame[0x0] = 0;
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frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4);
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frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2);
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frame[0x3] = format;
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frame[0x4] = channel_allocation;
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frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7);
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frame[0x6] = 0;
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frame[0x7] = 0;
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frame[0x8] = 0;
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frame[0x9] = 0;
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frame[0xA] = 0;
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r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
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WREG32(HDMI0_AUDIO_INFO0 + offset,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(HDMI0_AUDIO_INFO1 + offset,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
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}
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/*
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* test if audio buffer is filled enough to start playing
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*/
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static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
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}
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/*
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* have buffer status changed since last call?
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*/
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int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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int status, result;
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if (!dig->afmt || !dig->afmt->enabled)
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return 0;
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status = r600_hdmi_is_audio_buffer_filled(encoder);
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result = dig->afmt->last_buffer_filled_status != status;
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dig->afmt->last_buffer_filled_status = status;
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return result;
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}
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/*
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* write the audio workaround status to the hardware
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*/
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static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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bool hdmi_audio_workaround = false; /* FIXME */
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u32 value;
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if (!hdmi_audio_workaround ||
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r600_hdmi_is_audio_buffer_filled(encoder))
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value = 0; /* disable workaround */
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else
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value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
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WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
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value, ~HDMI0_AUDIO_TEST_EN);
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}
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/*
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* update the info frames with the data from the current display mode
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*/
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void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset;
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/* Silent, r600_hdmi_enable will raise WARN for us */
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if (!dig->afmt->enabled)
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return;
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offset = dig->afmt->offset;
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r600_audio_set_clock(encoder, mode->clock);
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND); /* send null packets when required */
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WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
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if (ASIC_IS_DCE32(rdev)) {
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WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
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HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
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HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
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WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
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AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
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AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
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} else {
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WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
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HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
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HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
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HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
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HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
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}
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WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
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HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
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HDMI0_ACR_SOURCE); /* select SW CTS value */
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND | /* send null packets when required */
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HDMI0_GC_SEND | /* send general control packets */
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HDMI0_GC_CONT); /* send general control packets every frame */
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/* TODO: HDMI0_AUDIO_INFO_UPDATE */
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WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
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HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
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HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
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HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
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HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
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WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
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HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
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HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
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WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
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r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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r600_hdmi_update_ACR(encoder, mode->clock);
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/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
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WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
|
|
WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
|
|
WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
|
|
WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
|
|
|
|
r600_hdmi_audio_workaround(encoder);
|
|
}
|
|
|
|
/*
|
|
* update settings with current parameters from audio engine
|
|
*/
|
|
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
|
struct r600_audio audio = r600_audio_status(rdev);
|
|
uint32_t offset;
|
|
uint32_t iec;
|
|
|
|
if (!dig->afmt || !dig->afmt->enabled)
|
|
return;
|
|
offset = dig->afmt->offset;
|
|
|
|
DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
|
|
r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
|
|
audio.channels, audio.rate, audio.bits_per_sample);
|
|
DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
|
|
(int)audio.status_bits, (int)audio.category_code);
|
|
|
|
iec = 0;
|
|
if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
|
|
iec |= 1 << 0;
|
|
if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
|
|
iec |= 1 << 1;
|
|
if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
|
|
iec |= 1 << 2;
|
|
if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
|
|
iec |= 1 << 3;
|
|
|
|
iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
|
|
|
|
switch (audio.rate) {
|
|
case 32000:
|
|
iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
|
|
break;
|
|
case 44100:
|
|
iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
|
|
break;
|
|
case 48000:
|
|
iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
|
|
break;
|
|
case 88200:
|
|
iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
|
|
break;
|
|
case 96000:
|
|
iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
|
|
break;
|
|
case 176400:
|
|
iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
|
|
break;
|
|
case 192000:
|
|
iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
|
|
break;
|
|
}
|
|
|
|
WREG32(HDMI0_60958_0 + offset, iec);
|
|
|
|
iec = 0;
|
|
switch (audio.bits_per_sample) {
|
|
case 16:
|
|
iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
|
|
break;
|
|
case 20:
|
|
iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
|
|
break;
|
|
case 24:
|
|
iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
|
|
break;
|
|
}
|
|
if (audio.status_bits & AUDIO_STATUS_V)
|
|
iec |= 0x5 << 16;
|
|
WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
|
|
|
|
r600_hdmi_audioinfoframe(encoder, audio.channels - 1, 0, 0, 0, 0, 0, 0,
|
|
0);
|
|
|
|
r600_hdmi_audio_workaround(encoder);
|
|
}
|
|
|
|
/*
|
|
* enable the HDMI engine
|
|
*/
|
|
void r600_hdmi_enable(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
|
uint32_t offset;
|
|
u32 hdmi;
|
|
|
|
if (ASIC_IS_DCE6(rdev))
|
|
return;
|
|
|
|
/* Silent, r600_hdmi_enable will raise WARN for us */
|
|
if (dig->afmt->enabled)
|
|
return;
|
|
offset = dig->afmt->offset;
|
|
|
|
/* Older chipsets require setting HDMI and routing manually */
|
|
if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
|
|
hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
|
|
switch (radeon_encoder->encoder_id) {
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
|
|
WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
|
|
~AVIVO_TMDSA_CNTL_HDMI_EN);
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
|
|
WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
|
|
~AVIVO_LVTMA_CNTL_HDMI_EN);
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_DDI:
|
|
WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
|
|
break;
|
|
default:
|
|
dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
|
|
radeon_encoder->encoder_id);
|
|
break;
|
|
}
|
|
WREG32(HDMI0_CONTROL + offset, hdmi);
|
|
}
|
|
|
|
if (rdev->irq.installed) {
|
|
/* if irq is available use it */
|
|
radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
|
|
}
|
|
|
|
dig->afmt->enabled = true;
|
|
|
|
DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
|
|
offset, radeon_encoder->encoder_id);
|
|
}
|
|
|
|
/*
|
|
* disable the HDMI engine
|
|
*/
|
|
void r600_hdmi_disable(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
|
uint32_t offset;
|
|
|
|
if (ASIC_IS_DCE6(rdev))
|
|
return;
|
|
|
|
/* Called for ATOM_ENCODER_MODE_HDMI only */
|
|
if (!dig || !dig->afmt) {
|
|
WARN_ON(1);
|
|
return;
|
|
}
|
|
if (!dig->afmt->enabled)
|
|
return;
|
|
offset = dig->afmt->offset;
|
|
|
|
DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
|
|
offset, radeon_encoder->encoder_id);
|
|
|
|
/* disable irq */
|
|
radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
|
|
|
|
/* Older chipsets not handled by AtomBIOS */
|
|
if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
|
|
switch (radeon_encoder->encoder_id) {
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
|
|
WREG32_P(AVIVO_TMDSA_CNTL, 0,
|
|
~AVIVO_TMDSA_CNTL_HDMI_EN);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
|
|
WREG32_P(AVIVO_LVTMA_CNTL, 0,
|
|
~AVIVO_LVTMA_CNTL_HDMI_EN);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_DDI:
|
|
WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
|
|
break;
|
|
default:
|
|
dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
|
|
radeon_encoder->encoder_id);
|
|
break;
|
|
}
|
|
WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);
|
|
}
|
|
|
|
dig->afmt->enabled = false;
|
|
}
|