![Paul Bolle](/assets/img/avatar_default.png)
Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
850 lines
24 KiB
C
850 lines
24 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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* Christian König
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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/*
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* IB
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* IBs (Indirect Buffers) and areas of GPU accessible memory where
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* commands are stored. You can put a pointer to the IB in the
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* command ring and the hw will fetch the commands from the IB
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* and execute them. Generally userspace acceleration drivers
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* produce command buffers which are send to the kernel and
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* put in IBs for execution by the requested ring.
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*/
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static int radeon_debugfs_sa_init(struct radeon_device *rdev);
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/**
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* radeon_ib_get - request an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ring: ring index the IB is associated with
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* @ib: IB object returned
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* @size: requested IB size
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*
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* Request an IB (all asics). IBs are allocated using the
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* suballocator.
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* Returns 0 on success, error on failure.
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*/
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int radeon_ib_get(struct radeon_device *rdev, int ring,
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struct radeon_ib *ib, struct radeon_vm *vm,
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unsigned size)
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{
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int i, r;
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r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
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if (r) {
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dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
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return r;
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}
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r = radeon_semaphore_create(rdev, &ib->semaphore);
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if (r) {
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return r;
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}
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ib->ring = ring;
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ib->fence = NULL;
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ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
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ib->vm = vm;
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if (vm) {
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/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
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* space and soffset is the offset inside the pool bo
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*/
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ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
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} else {
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ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
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}
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ib->is_const_ib = false;
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for (i = 0; i < RADEON_NUM_RINGS; ++i)
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ib->sync_to[i] = NULL;
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return 0;
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}
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/**
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* radeon_ib_free - free an IB (Indirect Buffer)
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to free
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*
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* Free an IB (all asics).
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*/
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
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radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
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radeon_fence_unref(&ib->fence);
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}
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/**
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* radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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* @const_ib: Const IB to schedule (SI only)
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*
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* Schedule an IB on the associated ring (all asics).
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* Returns 0 on success, error on failure.
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*
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* On SI, there are two parallel engines fed from the primary ring,
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* the CE (Constant Engine) and the DE (Drawing Engine). Since
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* resource descriptors have moved to memory, the CE allows you to
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* prime the caches while the DE is updating register state so that
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* the resource descriptors will be already in cache when the draw is
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* processed. To accomplish this, the userspace driver submits two
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* IBs, one for the CE and one for the DE. If there is a CE IB (called
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* a CONST_IB), it will be put on the ring prior to the DE IB. Prior
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* to SI there was just a DE IB.
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*/
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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struct radeon_ib *const_ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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bool need_sync = false;
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int i, r = 0;
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if (!ib->length_dw || !ring->ready) {
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/* TODO: Nothings in the ib we should report. */
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dev_err(rdev->dev, "couldn't schedule ib\n");
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return -EINVAL;
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}
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/* 64 dwords should be enough for fence too */
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r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
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if (r) {
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dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
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return r;
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}
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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struct radeon_fence *fence = ib->sync_to[i];
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if (radeon_fence_need_sync(fence, ib->ring)) {
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need_sync = true;
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radeon_semaphore_sync_rings(rdev, ib->semaphore,
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fence->ring, ib->ring);
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radeon_fence_note_sync(fence, ib->ring);
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}
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}
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/* immediately free semaphore when we don't need to sync */
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if (!need_sync) {
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radeon_semaphore_free(rdev, &ib->semaphore, NULL);
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}
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/* if we can't remember our last VM flush then flush now! */
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if (ib->vm && !ib->vm->last_flush) {
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radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
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}
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if (const_ib) {
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radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
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radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
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}
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radeon_ring_ib_execute(rdev, ib->ring, ib);
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r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
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if (r) {
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dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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if (const_ib) {
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const_ib->fence = radeon_fence_ref(ib->fence);
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}
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/* we just flushed the VM, remember that */
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if (ib->vm && !ib->vm->last_flush) {
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ib->vm->last_flush = radeon_fence_ref(ib->fence);
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}
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radeon_ring_unlock_commit(rdev, ring);
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return 0;
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}
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/**
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* radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
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*
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* @rdev: radeon_device pointer
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*
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* Initialize the suballocator to manage a pool of memory
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* for use as IBs (all asics).
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* Returns 0 on success, error on failure.
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*/
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int radeon_ib_pool_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->ib_pool_ready) {
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return 0;
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}
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r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
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RADEON_IB_POOL_SIZE*64*1024,
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RADEON_GEM_DOMAIN_GTT);
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if (r) {
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return r;
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}
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r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
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if (r) {
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return r;
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}
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rdev->ib_pool_ready = true;
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if (radeon_debugfs_sa_init(rdev)) {
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dev_err(rdev->dev, "failed to register debugfs file for SA\n");
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}
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return 0;
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}
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/**
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* radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
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*
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* @rdev: radeon_device pointer
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*
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* Tear down the suballocator managing the pool of memory
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* for use as IBs (all asics).
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*/
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void radeon_ib_pool_fini(struct radeon_device *rdev)
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{
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if (rdev->ib_pool_ready) {
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radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
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radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
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rdev->ib_pool_ready = false;
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}
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}
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/**
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* radeon_ib_ring_tests - test IBs on the rings
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*
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* @rdev: radeon_device pointer
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*
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* Test an IB (Indirect Buffer) on each ring.
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* If the test fails, disable the ring.
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* Returns 0 on success, error if the primary GFX ring
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* IB test fails.
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*/
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int radeon_ib_ring_tests(struct radeon_device *rdev)
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{
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unsigned i;
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int r;
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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struct radeon_ring *ring = &rdev->ring[i];
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if (!ring->ready)
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continue;
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r = radeon_ib_test(rdev, i, ring);
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if (r) {
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ring->ready = false;
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if (i == RADEON_RING_TYPE_GFX_INDEX) {
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/* oh, oh, that's really bad */
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DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
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rdev->accel_working = false;
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return r;
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} else {
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/* still not good, but we can live with it */
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DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
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}
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}
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}
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return 0;
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}
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/*
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* Rings
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* Most engines on the GPU are fed via ring buffers. Ring
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* buffers are areas of GPU accessible memory that the host
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* writes commands into and the GPU reads commands out of.
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* There is a rptr (read pointer) that determines where the
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* GPU is currently reading, and a wptr (write pointer)
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* which determines where the host has written. When the
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* pointers are equal, the ring is idle. When the host
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* writes commands to the ring buffer, it increments the
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* wptr. The GPU then starts fetching commands and executes
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* them until the pointers are equal again.
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*/
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static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
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/**
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* radeon_ring_write - write a value to the ring
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*
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* @ring: radeon_ring structure holding ring information
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* @v: dword (dw) value to write
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*
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* Write a value to the requested ring buffer (all asics).
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*/
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void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
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{
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#if DRM_DEBUG_CODE
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if (ring->count_dw <= 0) {
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DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
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}
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#endif
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ring->ring[ring->wptr++] = v;
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ring->wptr &= ring->ptr_mask;
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ring->count_dw--;
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ring->ring_free_dw--;
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}
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/**
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* radeon_ring_supports_scratch_reg - check if the ring supports
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* writing to scratch registers
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Check if a specific ring supports writing to scratch registers (all asics).
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* Returns true if the ring supports writing to scratch regs, false if not.
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*/
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bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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switch (ring->idx) {
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case RADEON_RING_TYPE_GFX_INDEX:
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case CAYMAN_RING_TYPE_CP1_INDEX:
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case CAYMAN_RING_TYPE_CP2_INDEX:
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return true;
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default:
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return false;
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}
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}
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/**
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* radeon_ring_free_size - update the free size
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Update the free dw slots in the ring buffer (all asics).
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*/
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void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 rptr;
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if (rdev->wb.enabled)
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rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
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else
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rptr = RREG32(ring->rptr_reg);
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ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
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/* This works because ring_size is a power of 2 */
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ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
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ring->ring_free_dw -= ring->wptr;
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ring->ring_free_dw &= ring->ptr_mask;
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if (!ring->ring_free_dw) {
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ring->ring_free_dw = ring->ring_size / 4;
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}
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}
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/**
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* radeon_ring_alloc - allocate space on the ring buffer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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* @ndw: number of dwords to allocate in the ring buffer
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*
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* Allocate @ndw dwords in the ring buffer (all asics).
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* Returns 0 on success, error on failure.
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*/
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int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
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{
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int r;
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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ndw = (ndw + ring->align_mask) & ~ring->align_mask;
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while (ndw > (ring->ring_free_dw - 1)) {
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radeon_ring_free_size(rdev, ring);
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if (ndw < ring->ring_free_dw) {
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break;
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}
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r = radeon_fence_wait_next_locked(rdev, ring->idx);
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if (r)
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return r;
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}
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ring->count_dw = ndw;
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ring->wptr_old = ring->wptr;
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return 0;
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}
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/**
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* radeon_ring_lock - lock the ring and allocate space on it
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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* @ndw: number of dwords to allocate in the ring buffer
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*
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* Lock the ring and allocate @ndw dwords in the ring buffer
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* (all asics).
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* Returns 0 on success, error on failure.
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*/
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int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
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{
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int r;
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mutex_lock(&rdev->ring_lock);
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r = radeon_ring_alloc(rdev, ring, ndw);
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if (r) {
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mutex_unlock(&rdev->ring_lock);
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return r;
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}
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return 0;
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}
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/**
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* radeon_ring_commit - tell the GPU to execute the new
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* commands on the ring buffer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Update the wptr (write pointer) to tell the GPU to
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* execute new commands on the ring buffer (all asics).
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*/
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void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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/* We pad to match fetch size */
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while (ring->wptr & ring->align_mask) {
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radeon_ring_write(ring, ring->nop);
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}
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DRM_MEMORYBARRIER();
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WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
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(void)RREG32(ring->wptr_reg);
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}
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/**
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* radeon_ring_unlock_commit - tell the GPU to execute the new
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* commands on the ring buffer and unlock it
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Call radeon_ring_commit() then unlock the ring (all asics).
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*/
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void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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radeon_ring_commit(rdev, ring);
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mutex_unlock(&rdev->ring_lock);
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}
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/**
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* radeon_ring_undo - reset the wptr
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*
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* @ring: radeon_ring structure holding ring information
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*
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* Reset the driver's copy of the wptr (all asics).
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*/
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void radeon_ring_undo(struct radeon_ring *ring)
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{
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ring->wptr = ring->wptr_old;
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}
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/**
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* radeon_ring_unlock_undo - reset the wptr and unlock the ring
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*
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* @ring: radeon_ring structure holding ring information
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*
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* Call radeon_ring_undo() then unlock the ring (all asics).
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*/
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void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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radeon_ring_undo(ring);
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mutex_unlock(&rdev->ring_lock);
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}
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/**
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* radeon_ring_force_activity - add some nop packets to the ring
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Add some nop packets to the ring to force activity (all asics).
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* Used for lockup detection to see if the rptr is advancing.
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|
*/
|
|
void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
|
|
{
|
|
int r;
|
|
|
|
radeon_ring_free_size(rdev, ring);
|
|
if (ring->rptr == ring->wptr) {
|
|
r = radeon_ring_alloc(rdev, ring, 1);
|
|
if (!r) {
|
|
radeon_ring_write(ring, ring->nop);
|
|
radeon_ring_commit(rdev, ring);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* radeon_ring_lockup_update - update lockup variables
|
|
*
|
|
* @ring: radeon_ring structure holding ring information
|
|
*
|
|
* Update the last rptr value and timestamp (all asics).
|
|
*/
|
|
void radeon_ring_lockup_update(struct radeon_ring *ring)
|
|
{
|
|
ring->last_rptr = ring->rptr;
|
|
ring->last_activity = jiffies;
|
|
}
|
|
|
|
/**
|
|
* radeon_ring_test_lockup() - check if ring is lockedup by recording information
|
|
* @rdev: radeon device structure
|
|
* @ring: radeon_ring structure holding ring information
|
|
*
|
|
* We don't need to initialize the lockup tracking information as we will either
|
|
* have CP rptr to a different value of jiffies wrap around which will force
|
|
* initialization of the lockup tracking informations.
|
|
*
|
|
* A possible false positivie is if we get call after while and last_cp_rptr ==
|
|
* the current CP rptr, even if it's unlikely it might happen. To avoid this
|
|
* if the elapsed time since last call is bigger than 2 second than we return
|
|
* false and update the tracking information. Due to this the caller must call
|
|
* radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
|
|
* the fencing code should be cautious about that.
|
|
*
|
|
* Caller should write to the ring to force CP to do something so we don't get
|
|
* false positive when CP is just gived nothing to do.
|
|
*
|
|
**/
|
|
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
|
|
{
|
|
unsigned long cjiffies, elapsed;
|
|
uint32_t rptr;
|
|
|
|
cjiffies = jiffies;
|
|
if (!time_after(cjiffies, ring->last_activity)) {
|
|
/* likely a wrap around */
|
|
radeon_ring_lockup_update(ring);
|
|
return false;
|
|
}
|
|
rptr = RREG32(ring->rptr_reg);
|
|
ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
|
|
if (ring->rptr != ring->last_rptr) {
|
|
/* CP is still working no lockup */
|
|
radeon_ring_lockup_update(ring);
|
|
return false;
|
|
}
|
|
elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
|
|
if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
|
|
dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
|
|
return true;
|
|
}
|
|
/* give a chance to the GPU ... */
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* radeon_ring_backup - Back up the content of a ring
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @ring: the ring we want to back up
|
|
*
|
|
* Saves all unprocessed commits from a ring, returns the number of dwords saved.
|
|
*/
|
|
unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
|
|
uint32_t **data)
|
|
{
|
|
unsigned size, ptr, i;
|
|
|
|
/* just in case lock the ring */
|
|
mutex_lock(&rdev->ring_lock);
|
|
*data = NULL;
|
|
|
|
if (ring->ring_obj == NULL) {
|
|
mutex_unlock(&rdev->ring_lock);
|
|
return 0;
|
|
}
|
|
|
|
/* it doesn't make sense to save anything if all fences are signaled */
|
|
if (!radeon_fence_count_emitted(rdev, ring->idx)) {
|
|
mutex_unlock(&rdev->ring_lock);
|
|
return 0;
|
|
}
|
|
|
|
/* calculate the number of dw on the ring */
|
|
if (ring->rptr_save_reg)
|
|
ptr = RREG32(ring->rptr_save_reg);
|
|
else if (rdev->wb.enabled)
|
|
ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
|
|
else {
|
|
/* no way to read back the next rptr */
|
|
mutex_unlock(&rdev->ring_lock);
|
|
return 0;
|
|
}
|
|
|
|
size = ring->wptr + (ring->ring_size / 4);
|
|
size -= ptr;
|
|
size &= ring->ptr_mask;
|
|
if (size == 0) {
|
|
mutex_unlock(&rdev->ring_lock);
|
|
return 0;
|
|
}
|
|
|
|
/* and then save the content of the ring */
|
|
*data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
|
|
if (!*data) {
|
|
mutex_unlock(&rdev->ring_lock);
|
|
return 0;
|
|
}
|
|
for (i = 0; i < size; ++i) {
|
|
(*data)[i] = ring->ring[ptr++];
|
|
ptr &= ring->ptr_mask;
|
|
}
|
|
|
|
mutex_unlock(&rdev->ring_lock);
|
|
return size;
|
|
}
|
|
|
|
/**
|
|
* radeon_ring_restore - append saved commands to the ring again
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @ring: ring to append commands to
|
|
* @size: number of dwords we want to write
|
|
* @data: saved commands
|
|
*
|
|
* Allocates space on the ring and restore the previously saved commands.
|
|
*/
|
|
int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
|
|
unsigned size, uint32_t *data)
|
|
{
|
|
int i, r;
|
|
|
|
if (!size || !data)
|
|
return 0;
|
|
|
|
/* restore the saved ring content */
|
|
r = radeon_ring_lock(rdev, ring, size);
|
|
if (r)
|
|
return r;
|
|
|
|
for (i = 0; i < size; ++i) {
|
|
radeon_ring_write(ring, data[i]);
|
|
}
|
|
|
|
radeon_ring_unlock_commit(rdev, ring);
|
|
kfree(data);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_ring_init - init driver ring struct.
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @ring: radeon_ring structure holding ring information
|
|
* @ring_size: size of the ring
|
|
* @rptr_offs: offset of the rptr writeback location in the WB buffer
|
|
* @rptr_reg: MMIO offset of the rptr register
|
|
* @wptr_reg: MMIO offset of the wptr register
|
|
* @ptr_reg_shift: bit offset of the rptr/wptr values
|
|
* @ptr_reg_mask: bit mask of the rptr/wptr values
|
|
* @nop: nop packet for this ring
|
|
*
|
|
* Initialize the driver information for the selected ring (all asics).
|
|
* Returns 0 on success, error on failure.
|
|
*/
|
|
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
|
|
unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
|
|
u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
|
|
{
|
|
int r;
|
|
|
|
ring->ring_size = ring_size;
|
|
ring->rptr_offs = rptr_offs;
|
|
ring->rptr_reg = rptr_reg;
|
|
ring->wptr_reg = wptr_reg;
|
|
ring->ptr_reg_shift = ptr_reg_shift;
|
|
ring->ptr_reg_mask = ptr_reg_mask;
|
|
ring->nop = nop;
|
|
/* Allocate ring buffer */
|
|
if (ring->ring_obj == NULL) {
|
|
r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
|
|
RADEON_GEM_DOMAIN_GTT,
|
|
NULL, &ring->ring_obj);
|
|
if (r) {
|
|
dev_err(rdev->dev, "(%d) ring create failed\n", r);
|
|
return r;
|
|
}
|
|
r = radeon_bo_reserve(ring->ring_obj, false);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
|
|
&ring->gpu_addr);
|
|
if (r) {
|
|
radeon_bo_unreserve(ring->ring_obj);
|
|
dev_err(rdev->dev, "(%d) ring pin failed\n", r);
|
|
return r;
|
|
}
|
|
r = radeon_bo_kmap(ring->ring_obj,
|
|
(void **)&ring->ring);
|
|
radeon_bo_unreserve(ring->ring_obj);
|
|
if (r) {
|
|
dev_err(rdev->dev, "(%d) ring map failed\n", r);
|
|
return r;
|
|
}
|
|
}
|
|
ring->ptr_mask = (ring->ring_size / 4) - 1;
|
|
ring->ring_free_dw = ring->ring_size / 4;
|
|
if (rdev->wb.enabled) {
|
|
u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
|
|
ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
|
|
ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
|
|
}
|
|
if (radeon_debugfs_ring_init(rdev, ring)) {
|
|
DRM_ERROR("Failed to register debugfs file for rings !\n");
|
|
}
|
|
radeon_ring_lockup_update(ring);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_ring_fini - tear down the driver ring struct.
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @ring: radeon_ring structure holding ring information
|
|
*
|
|
* Tear down the driver information for the selected ring (all asics).
|
|
*/
|
|
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
|
|
{
|
|
int r;
|
|
struct radeon_bo *ring_obj;
|
|
|
|
mutex_lock(&rdev->ring_lock);
|
|
ring_obj = ring->ring_obj;
|
|
ring->ready = false;
|
|
ring->ring = NULL;
|
|
ring->ring_obj = NULL;
|
|
mutex_unlock(&rdev->ring_lock);
|
|
|
|
if (ring_obj) {
|
|
r = radeon_bo_reserve(ring_obj, false);
|
|
if (likely(r == 0)) {
|
|
radeon_bo_kunmap(ring_obj);
|
|
radeon_bo_unpin(ring_obj);
|
|
radeon_bo_unreserve(ring_obj);
|
|
}
|
|
radeon_bo_unref(&ring_obj);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Debugfs info
|
|
*/
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
int ridx = *(int*)node->info_ent->data;
|
|
struct radeon_ring *ring = &rdev->ring[ridx];
|
|
unsigned count, i, j;
|
|
|
|
radeon_ring_free_size(rdev, ring);
|
|
count = (ring->ring_size / 4) - ring->ring_free_dw;
|
|
seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
|
|
seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
|
|
if (ring->rptr_save_reg) {
|
|
seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
|
|
RREG32(ring->rptr_save_reg));
|
|
}
|
|
seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
|
|
seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
|
|
seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
|
|
seq_printf(m, "%u dwords in ring\n", count);
|
|
i = ring->rptr;
|
|
for (j = 0; j <= count; j++) {
|
|
seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
|
|
i = (i + 1) & ring->ptr_mask;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
|
|
static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
|
|
static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
|
|
|
|
static struct drm_info_list radeon_debugfs_ring_info_list[] = {
|
|
{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
|
|
{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
|
|
{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
|
|
};
|
|
|
|
static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static struct drm_info_list radeon_debugfs_sa_list[] = {
|
|
{"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
|
|
};
|
|
|
|
#endif
|
|
|
|
static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
unsigned i;
|
|
for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
|
|
struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
|
|
int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
|
|
unsigned r;
|
|
|
|
if (&rdev->ring[ridx] != ring)
|
|
continue;
|
|
|
|
r = radeon_debugfs_add_files(rdev, info, 1);
|
|
if (r)
|
|
return r;
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_debugfs_sa_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|