![Linus Walleij](/assets/img/avatar_default.png)
The Nomadik variant has a few special quirks that need to be respected to make the driver work: - The block need to be clocked during writing of the TIMn registers or the bus will stall. - Special bits in the control register select how many of the output display lines get activated. - Special bits in the control register select how to manage the different 565 and 5551 modes. - There is a packed 24bit graphics mode, i.e 888 pixels can be stored in memory is three consecutive bytes, not evenly aligned to a 32bit word. This patch uses the vendor data pointer from the AMBA matching mechanism to track the quirks for this variant, and adds two hooks that variants can use to initialize boards and panels during start-up. These will later be used to adopt a Nomadik board profile. Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
388 lines
9.8 KiB
C
388 lines
9.8 KiB
C
/*
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* linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
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*
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* David A Rusling
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*
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* Copyright (C) 2001 ARM Limited
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/fb.h>
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/*
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* CLCD Controller Internal Register addresses
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*/
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#define CLCD_TIM0 0x00000000
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#define CLCD_TIM1 0x00000004
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#define CLCD_TIM2 0x00000008
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#define CLCD_TIM3 0x0000000c
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#define CLCD_UBAS 0x00000010
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#define CLCD_LBAS 0x00000014
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#define CLCD_PL110_IENB 0x00000018
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#define CLCD_PL110_CNTL 0x0000001c
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#define CLCD_PL110_STAT 0x00000020
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#define CLCD_PL110_INTR 0x00000024
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#define CLCD_PL110_UCUR 0x00000028
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#define CLCD_PL110_LCUR 0x0000002C
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#define CLCD_PL111_CNTL 0x00000018
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#define CLCD_PL111_IENB 0x0000001c
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#define CLCD_PL111_RIS 0x00000020
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#define CLCD_PL111_MIS 0x00000024
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#define CLCD_PL111_ICR 0x00000028
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#define CLCD_PL111_UCUR 0x0000002c
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#define CLCD_PL111_LCUR 0x00000030
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#define CLCD_PALL 0x00000200
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#define CLCD_PALETTE 0x00000200
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#define TIM2_CLKSEL (1 << 5)
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#define TIM2_IVS (1 << 11)
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#define TIM2_IHS (1 << 12)
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#define TIM2_IPC (1 << 13)
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#define TIM2_IOE (1 << 14)
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#define TIM2_BCD (1 << 26)
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#define CNTL_LCDEN (1 << 0)
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#define CNTL_LCDBPP1 (0 << 1)
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#define CNTL_LCDBPP2 (1 << 1)
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#define CNTL_LCDBPP4 (2 << 1)
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#define CNTL_LCDBPP8 (3 << 1)
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#define CNTL_LCDBPP16 (4 << 1)
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#define CNTL_LCDBPP16_565 (6 << 1)
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#define CNTL_LCDBPP16_444 (7 << 1)
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#define CNTL_LCDBPP24 (5 << 1)
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#define CNTL_LCDBW (1 << 4)
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#define CNTL_LCDTFT (1 << 5)
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#define CNTL_LCDMONO8 (1 << 6)
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#define CNTL_LCDDUAL (1 << 7)
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#define CNTL_BGR (1 << 8)
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#define CNTL_BEBO (1 << 9)
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#define CNTL_BEPO (1 << 10)
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#define CNTL_LCDPWR (1 << 11)
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#define CNTL_LCDVCOMP(x) ((x) << 12)
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#define CNTL_LDMAFIFOTIME (1 << 15)
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#define CNTL_WATERMARK (1 << 16)
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/* ST Microelectronics variant bits */
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#define CNTL_ST_1XBPP_444 0x0
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#define CNTL_ST_1XBPP_5551 (1 << 17)
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#define CNTL_ST_1XBPP_565 (1 << 18)
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#define CNTL_ST_CDWID_12 0x0
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#define CNTL_ST_CDWID_16 (1 << 19)
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#define CNTL_ST_CDWID_18 (1 << 20)
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#define CNTL_ST_CDWID_24 ((1 << 19)|(1 << 20))
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#define CNTL_ST_CEAEN (1 << 21)
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#define CNTL_ST_LCDBPP24_PACKED (6 << 1)
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enum {
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/* individual formats */
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CLCD_CAP_RGB444 = (1 << 0),
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CLCD_CAP_RGB5551 = (1 << 1),
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CLCD_CAP_RGB565 = (1 << 2),
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CLCD_CAP_RGB888 = (1 << 3),
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CLCD_CAP_BGR444 = (1 << 4),
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CLCD_CAP_BGR5551 = (1 << 5),
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CLCD_CAP_BGR565 = (1 << 6),
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CLCD_CAP_BGR888 = (1 << 7),
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/* connection layouts */
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CLCD_CAP_444 = CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
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CLCD_CAP_5551 = CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
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CLCD_CAP_565 = CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
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CLCD_CAP_888 = CLCD_CAP_RGB888 | CLCD_CAP_BGR888,
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/* red/blue ordering */
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CLCD_CAP_RGB = CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
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CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
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CLCD_CAP_BGR = CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
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CLCD_CAP_BGR565 | CLCD_CAP_BGR888,
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CLCD_CAP_ALL = CLCD_CAP_BGR | CLCD_CAP_RGB,
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};
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struct backlight_device;
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struct clcd_panel {
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struct fb_videomode mode;
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signed short width; /* width in mm */
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signed short height; /* height in mm */
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u32 tim2;
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u32 tim3;
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u32 cntl;
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u32 caps;
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unsigned int bpp:8,
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fixedtimings:1,
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grayscale:1;
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unsigned int connector;
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struct backlight_device *backlight;
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/*
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* If the B/R lines are switched between the CLCD
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* and the panel we need to know this and not try to
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* compensate with the BGR bit in the control register.
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*/
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bool bgr_connection;
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};
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struct clcd_regs {
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u32 tim0;
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u32 tim1;
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u32 tim2;
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u32 tim3;
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u32 cntl;
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unsigned long pixclock;
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};
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struct clcd_fb;
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/*
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* the board-type specific routines
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*/
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struct clcd_board {
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const char *name;
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/*
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* Optional. Hardware capability flags.
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*/
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u32 caps;
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/*
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* Optional. Check whether the var structure is acceptable
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* for this display.
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*/
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int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
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/*
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* Compulsory. Decode fb->fb.var into regs->*. In the case of
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* fixed timing, set regs->* to the register values required.
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*/
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void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
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/*
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* Optional. Disable any extra display hardware.
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*/
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void (*disable)(struct clcd_fb *);
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/*
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* Optional. Enable any extra display hardware.
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*/
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void (*enable)(struct clcd_fb *);
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/*
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* Setup platform specific parts of CLCD driver
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*/
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int (*setup)(struct clcd_fb *);
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/*
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* mmap the framebuffer memory
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*/
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int (*mmap)(struct clcd_fb *, struct vm_area_struct *);
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/*
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* Remove platform specific parts of CLCD driver
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*/
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void (*remove)(struct clcd_fb *);
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};
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struct amba_device;
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struct clk;
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/**
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* struct clcd_vendor_data - holds hardware (IP-block) vendor-specific
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* variant information
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*
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* @clock_timregs: the CLCD needs to be clocked when accessing the
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* timer registers, or the hardware will hang.
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* @packed_24_bit_pixels: this variant supports 24bit packed pixel data,
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* so that RGB accesses 3 bytes at a time, not just on even 32bit
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* boundaries, packing the pixel data in memory. ST Microelectronics
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* have this.
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* @st_bitmux_control: ST Microelectronics have implemented output
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* bit line multiplexing into the CLCD control register. This indicates
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* that we need to use this.
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* @init_board: custom board init function for this variant
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* @init_panel: custom panel init function for this variant
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*/
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struct clcd_vendor_data {
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bool clock_timregs;
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bool packed_24_bit_pixels;
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bool st_bitmux_control;
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int (*init_board)(struct amba_device *adev,
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struct clcd_board *board);
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int (*init_panel)(struct clcd_fb *fb,
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struct device_node *panel);
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};
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/* this data structure describes each frame buffer device we find */
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struct clcd_fb {
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struct fb_info fb;
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struct amba_device *dev;
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struct clk *clk;
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struct clcd_vendor_data *vendor;
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struct clcd_panel *panel;
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struct clcd_board *board;
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void *board_data;
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void __iomem *regs;
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u16 off_ienb;
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u16 off_cntl;
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u32 clcd_cntl;
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u32 cmap[16];
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bool clk_enabled;
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};
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static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
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{
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struct fb_var_screeninfo *var = &fb->fb.var;
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u32 val, cpl;
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/*
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* Program the CLCD controller registers and start the CLCD
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*/
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val = ((var->xres / 16) - 1) << 2;
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val |= (var->hsync_len - 1) << 8;
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val |= (var->right_margin - 1) << 16;
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val |= (var->left_margin - 1) << 24;
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regs->tim0 = val;
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val = var->yres;
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if (fb->panel->cntl & CNTL_LCDDUAL)
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val /= 2;
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val -= 1;
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val |= (var->vsync_len - 1) << 10;
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val |= var->lower_margin << 16;
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val |= var->upper_margin << 24;
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regs->tim1 = val;
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val = fb->panel->tim2;
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val |= var->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
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val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
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cpl = var->xres_virtual;
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if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
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/* / 1 */;
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else if (!var->grayscale) /* STN color */
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cpl = cpl * 8 / 3;
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else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
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cpl /= 8;
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else /* STN monochrome, 4bit */
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cpl /= 4;
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regs->tim2 = val | ((cpl - 1) << 16);
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regs->tim3 = fb->panel->tim3;
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val = fb->panel->cntl;
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if (var->grayscale)
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val |= CNTL_LCDBW;
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if (fb->panel->caps && fb->board->caps && var->bits_per_pixel >= 16) {
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/*
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* if board and panel supply capabilities, we can support
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* changing BGR/RGB depending on supplied parameters. Here
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* we switch to what the framebuffer is providing if need
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* be, so if the framebuffer is BGR but the display connection
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* is RGB (first case) we switch it around. Vice versa mutatis
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* mutandis if the framebuffer is RGB but the display connection
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* is BGR, we flip it around.
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*/
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if (var->red.offset == 0)
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val &= ~CNTL_BGR;
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else
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val |= CNTL_BGR;
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if (fb->panel->bgr_connection)
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val ^= CNTL_BGR;
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}
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switch (var->bits_per_pixel) {
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case 1:
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val |= CNTL_LCDBPP1;
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break;
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case 2:
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val |= CNTL_LCDBPP2;
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break;
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case 4:
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val |= CNTL_LCDBPP4;
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break;
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case 8:
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val |= CNTL_LCDBPP8;
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break;
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case 16:
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/*
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* PL110 cannot choose between 5551 and 565 modes in its
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* control register. It is possible to use 565 with
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* custom external wiring.
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*/
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if (amba_part(fb->dev) == 0x110 ||
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var->green.length == 5)
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val |= CNTL_LCDBPP16;
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else if (var->green.length == 6)
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val |= CNTL_LCDBPP16_565;
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else
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val |= CNTL_LCDBPP16_444;
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break;
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case 24:
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/* Modified variant supporting 24 bit packed pixels */
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val |= CNTL_ST_LCDBPP24_PACKED;
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break;
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case 32:
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val |= CNTL_LCDBPP24;
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break;
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}
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regs->cntl = val;
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regs->pixclock = var->pixclock;
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}
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static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
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{
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var->xres_virtual = var->xres = (var->xres + 15) & ~15;
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var->yres_virtual = var->yres = (var->yres + 1) & ~1;
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#define CHECK(e,l,h) (var->e < l || var->e > h)
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if (CHECK(right_margin, (5+1), 256) || /* back porch */
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CHECK(left_margin, (5+1), 256) || /* front porch */
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CHECK(hsync_len, (5+1), 256) ||
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var->xres > 4096 ||
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var->lower_margin > 255 || /* back porch */
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var->upper_margin > 255 || /* front porch */
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var->vsync_len > 32 ||
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var->yres > 1024)
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return -EINVAL;
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#undef CHECK
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/* single panel mode: PCD = max(PCD, 1) */
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/* dual panel mode: PCD = max(PCD, 5) */
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/*
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* You can't change the grayscale setting, and
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* we can only do non-interlaced video.
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*/
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if (var->grayscale != fb->fb.var.grayscale ||
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(var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
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return -EINVAL;
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#define CHECK(e) (var->e != fb->fb.var.e)
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if (fb->panel->fixedtimings &&
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(CHECK(xres) ||
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CHECK(yres) ||
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CHECK(bits_per_pixel) ||
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CHECK(pixclock) ||
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CHECK(left_margin) ||
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CHECK(right_margin) ||
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CHECK(upper_margin) ||
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CHECK(lower_margin) ||
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CHECK(hsync_len) ||
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CHECK(vsync_len) ||
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CHECK(sync)))
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return -EINVAL;
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#undef CHECK
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var->nonstd = 0;
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var->accel_flags = 0;
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return 0;
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}
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