687ee0ad4e
Pull networking updates from David Miller:
1) BBR TCP congestion control, from Neal Cardwell, Yuchung Cheng and
co. at Google. https://lwn.net/Articles/701165/
2) Do TCP Small Queues for retransmits, from Eric Dumazet.
3) Support collect_md mode for all IPV4 and IPV6 tunnels, from Alexei
Starovoitov.
4) Allow cls_flower to classify packets in ip tunnels, from Amir Vadai.
5) Support DSA tagging in older mv88e6xxx switches, from Andrew Lunn.
6) Support GMAC protocol in iwlwifi mwm, from Ayala Beker.
7) Support ndo_poll_controller in mlx5, from Calvin Owens.
8) Move VRF processing to an output hook and allow l3mdev to be
loopback, from David Ahern.
9) Support SOCK_DESTROY for UDP sockets. Also from David Ahern.
10) Congestion control in RXRPC, from David Howells.
11) Support geneve RX offload in ixgbe, from Emil Tantilov.
12) When hitting pressure for new incoming TCP data SKBs, perform a
partial rathern than a full purge of the OFO queue (which could be
huge). From Eric Dumazet.
13) Convert XFRM state and policy lookups to RCU, from Florian Westphal.
14) Support RX network flow classification to igb, from Gangfeng Huang.
15) Hardware offloading of eBPF in nfp driver, from Jakub Kicinski.
16) New skbmod packet action, from Jamal Hadi Salim.
17) Remove some inefficiencies in snmp proc output, from Jia He.
18) Add FIB notifications to properly propagate route changes to
hardware which is doing forwarding offloading. From Jiri Pirko.
19) New dsa driver for qca8xxx chips, from John Crispin.
20) Implement RFC7559 ipv6 router solicitation backoff, from Maciej
Żenczykowski.
21) Add L3 mode to ipvlan, from Mahesh Bandewar.
22) Support 802.1ad in mlx4, from Moshe Shemesh.
23) Support hardware LRO in mediatek driver, from Nelson Chang.
24) Add TC offloading to mlx5, from Or Gerlitz.
25) Convert various drivers to ethtool ksettings interfaces, from
Philippe Reynes.
26) TX max rate limiting for cxgb4, from Rahul Lakkireddy.
27) NAPI support for ath10k, from Rajkumar Manoharan.
28) Support XDP in mlx5, from Rana Shahout and Saeed Mahameed.
29) UDP replicast support in TIPC, from Richard Alpe.
30) Per-queue statistics for qed driver, from Sudarsana Reddy Kalluru.
31) Support BQL in thunderx driver, from Sunil Goutham.
32) TSO support in alx driver, from Tobias Regnery.
33) Add stream parser engine and use it in kcm.
34) Support async DHCP replies in ipconfig module, from Uwe
Kleine-König.
35) DSA port fast aging for mv88e6xxx driver, from Vivien Didelot.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1715 commits)
mlxsw: switchx2: Fix misuse of hard_header_len
mlxsw: spectrum: Fix misuse of hard_header_len
net/faraday: Stop NCSI device on shutdown
net/ncsi: Introduce ncsi_stop_dev()
net/ncsi: Rework the channel monitoring
net/ncsi: Allow to extend NCSI request properties
net/ncsi: Rework request index allocation
net/ncsi: Don't probe on the reserved channel ID (0x1f)
net/ncsi: Introduce NCSI_RESERVED_CHANNEL
net/ncsi: Avoid unused-value build warning from ia64-linux-gcc
net: Add netdev all_adj_list refcnt propagation to fix panic
net: phy: Add Edge-rate driver for Microsemi PHYs.
vmxnet3: Wake queue from reset work
i40e: avoid NULL pointer dereference and recursive errors on early PCI error
qed: Add RoCE ll2 & GSI support
qed: Add support for memory registeration verbs
qed: Add support for QP verbs
qed: PD,PKEY and CQ verb support
qed: Add support for RoCE hw init
qede: Add qedr framework
...
104 lines
5 KiB
C
104 lines
5 KiB
C
#ifndef LINUX_BCMA_REGS_H_
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#define LINUX_BCMA_REGS_H_
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/* Some single registers are shared between many cores */
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/* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
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#define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
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#define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
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#define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
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#define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
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#define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
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#define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
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#define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
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#define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
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#define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
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#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
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#define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
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#define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
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#define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
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#define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
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#define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
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#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
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/* Is there any BCM4328 on BCMA bus? */
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#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
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#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
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/* Agent registers (common for every core) */
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#define BCMA_OOB_SEL_OUT_A30 0x0100
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#define BCMA_IOCTL 0x0408 /* IO control */
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#define BCMA_IOCTL_CLK 0x0001
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#define BCMA_IOCTL_FGC 0x0002
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#define BCMA_IOCTL_CORE_BITS 0x3FFC
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#define BCMA_IOCTL_PME_EN 0x4000
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#define BCMA_IOCTL_BIST_EN 0x8000
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#define BCMA_IOST 0x0500 /* IO status */
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#define BCMA_IOST_CORE_BITS 0x0FFF
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#define BCMA_IOST_DMA64 0x1000
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#define BCMA_IOST_GATED_CLK 0x2000
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#define BCMA_IOST_BIST_ERROR 0x4000
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#define BCMA_IOST_BIST_DONE 0x8000
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#define BCMA_RESET_CTL 0x0800
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#define BCMA_RESET_CTL_RESET 0x0001
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#define BCMA_RESET_ST 0x0804
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#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
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#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
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#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
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#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
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/* BCMA PCI config space registers. */
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#define BCMA_PCI_PMCSR 0x44
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#define BCMA_PCI_PE 0x100
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#define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */
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#define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */
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#define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */
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#define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */
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#define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */
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#define BCMA_PCI_IRQS 0x90 /* PCI interrupts */
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#define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
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#define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
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#define BCMA_PCI_BAR0_WIN2 0xAC
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#define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
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#define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
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#define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
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#define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
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#define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
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#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
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#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
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#define BCMA_PCIE2_BAR0_WIN2 0x70
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/* SiliconBackplane Address Map.
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* All regions may not exist on all chips.
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*/
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#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
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#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
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#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
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#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
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#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
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#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
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#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
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#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
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#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
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#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
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* (2 ZettaBytes), low 32 bits
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*/
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#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
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* (2 ZettaBytes), high 32 bits
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*/
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#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
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#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
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#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
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* (2 ZettaBytes), high 32 bits
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*/
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#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
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#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
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#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
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#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
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#endif /* LINUX_BCMA_REGS_H_ */
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