d29633b40e
Clean up the boot sequence code & fix the following issues: 1. Always read the registers' values and set the relevant bits instead of zeroing all other bits 2. Handle cases where wl1271_top_reg_read returns an error 3. Verify that the HW can detect the selected clock source 4. Remove 128x PG10 initialization code 5. Configure the MCS PLL to work in HP mode Signed-off-by: Ido Yariv <ido@wizery.com> Reviewed-by: Luciano Coelho <coelho@ti.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
75 lines
2 KiB
C
75 lines
2 KiB
C
/*
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* This file is part of wl12xx
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef _LINUX_WL12XX_H
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#define _LINUX_WL12XX_H
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/* Reference clock values */
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enum {
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WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
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WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
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WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
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WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
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WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
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WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
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};
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/* TCXO clock values */
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enum {
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WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
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WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
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WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
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WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
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WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */
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WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */
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WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */
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WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */
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};
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struct wl12xx_platform_data {
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void (*set_power)(bool enable);
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/* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */
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int irq;
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bool use_eeprom;
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int board_ref_clock;
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int board_tcxo_clock;
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};
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#ifdef CONFIG_WL12XX_PLATFORM_DATA
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int wl12xx_set_platform_data(const struct wl12xx_platform_data *data);
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#else
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static inline
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int wl12xx_set_platform_data(const struct wl12xx_platform_data *data)
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{
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return -ENOSYS;
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}
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#endif
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const struct wl12xx_platform_data *wl12xx_get_platform_data(void);
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#endif
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