![David Brownell](/assets/img/avatar_default.png)
This adds a quirk to the OHCI driver that lets it work with an old Compaq implementation. It also removes some needless strings from the non-debug version of the driver. Signed-off-by: Chris Clayton <chris_clayton@f1internet.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
1117 lines
31 KiB
C
1117 lines
31 KiB
C
/*
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* OHCI HCD (Host Controller Driver) for USB.
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*
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
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*
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* This file is licenced under the GPL.
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*/
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static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
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{
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int last = urb_priv->length - 1;
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if (last >= 0) {
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int i;
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struct td *td;
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for (i = 0; i <= last; i++) {
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td = urb_priv->td [i];
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if (td)
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td_free (hc, td);
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}
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}
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list_del (&urb_priv->pending);
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kfree (urb_priv);
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}
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/*-------------------------------------------------------------------------*/
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/*
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* URB goes back to driver, and isn't reissued.
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* It's completely gone from HC data structures.
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* PRECONDITION: ohci lock held, irqs blocked.
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*/
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static void
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finish_urb (struct ohci_hcd *ohci, struct urb *urb, struct pt_regs *regs)
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__releases(ohci->lock)
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__acquires(ohci->lock)
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{
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// ASSERT (urb->hcpriv != 0);
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urb_free_priv (ohci, urb->hcpriv);
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urb->hcpriv = NULL;
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spin_lock (&urb->lock);
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if (likely (urb->status == -EINPROGRESS))
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urb->status = 0;
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/* report short control reads right even though the data TD always
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* has TD_R set. (much simpler, but creates the 1-td limit.)
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*/
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if (unlikely (urb->transfer_flags & URB_SHORT_NOT_OK)
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&& unlikely (usb_pipecontrol (urb->pipe))
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&& urb->actual_length < urb->transfer_buffer_length
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&& usb_pipein (urb->pipe)
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&& urb->status == 0) {
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urb->status = -EREMOTEIO;
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}
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spin_unlock (&urb->lock);
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switch (usb_pipetype (urb->pipe)) {
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case PIPE_ISOCHRONOUS:
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ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
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break;
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case PIPE_INTERRUPT:
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ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
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break;
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}
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#ifdef OHCI_VERBOSE_DEBUG
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urb_print (urb, "RET", usb_pipeout (urb->pipe));
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#endif
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/* urb->complete() can reenter this HCD */
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spin_unlock (&ohci->lock);
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usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb, regs);
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spin_lock (&ohci->lock);
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/* stop periodic dma if it's not needed */
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if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
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&& ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
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ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
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ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
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}
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}
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/*-------------------------------------------------------------------------*
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* ED handling functions
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*-------------------------------------------------------------------------*/
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/* search for the right schedule branch to use for a periodic ed.
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* does some load balancing; returns the branch, or negative errno.
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*/
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static int balance (struct ohci_hcd *ohci, int interval, int load)
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{
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int i, branch = -ENOSPC;
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/* iso periods can be huge; iso tds specify frame numbers */
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if (interval > NUM_INTS)
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interval = NUM_INTS;
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/* search for the least loaded schedule branch of that period
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* that has enough bandwidth left unreserved.
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*/
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for (i = 0; i < interval ; i++) {
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if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
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#if 1 /* CONFIG_USB_BANDWIDTH */
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int j;
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/* usb 1.1 says 90% of one frame */
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for (j = i; j < NUM_INTS; j += interval) {
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if ((ohci->load [j] + load) > 900)
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break;
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}
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if (j < NUM_INTS)
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continue;
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#endif
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branch = i;
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}
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}
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return branch;
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}
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/*-------------------------------------------------------------------------*/
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/* both iso and interrupt requests have periods; this routine puts them
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* into the schedule tree in the apppropriate place. most iso devices use
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* 1msec periods, but that's not required.
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*/
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static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
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{
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unsigned i;
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ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
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(ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
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ed, ed->branch, ed->load, ed->interval);
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for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
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struct ed **prev = &ohci->periodic [i];
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__hc32 *prev_p = &ohci->hcca->int_table [i];
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struct ed *here = *prev;
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/* sorting each branch by period (slow before fast)
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* lets us share the faster parts of the tree.
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* (plus maybe: put interrupt eds before iso)
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*/
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while (here && ed != here) {
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if (ed->interval > here->interval)
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break;
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prev = &here->ed_next;
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prev_p = &here->hwNextED;
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here = *prev;
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}
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if (ed != here) {
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ed->ed_next = here;
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if (here)
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ed->hwNextED = *prev_p;
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wmb ();
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*prev = ed;
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*prev_p = cpu_to_hc32(ohci, ed->dma);
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wmb();
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}
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ohci->load [i] += ed->load;
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}
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ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
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}
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/* link an ed into one of the HC chains */
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static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
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{
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int branch;
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if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING)
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return -EAGAIN;
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ed->state = ED_OPER;
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ed->ed_prev = NULL;
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ed->ed_next = NULL;
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ed->hwNextED = 0;
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wmb ();
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/* we care about rm_list when setting CLE/BLE in case the HC was at
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* work on some TD when CLE/BLE was turned off, and isn't quiesced
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* yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
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*
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* control and bulk EDs are doubly linked (ed_next, ed_prev), but
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* periodic ones are singly linked (ed_next). that's because the
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* periodic schedule encodes a tree like figure 3-5 in the ohci
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* spec: each qh can have several "previous" nodes, and the tree
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* doesn't have unused/idle descriptors.
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*/
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switch (ed->type) {
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case PIPE_CONTROL:
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if (ohci->ed_controltail == NULL) {
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WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
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ohci_writel (ohci, ed->dma,
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&ohci->regs->ed_controlhead);
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} else {
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ohci->ed_controltail->ed_next = ed;
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ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
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ed->dma);
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}
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ed->ed_prev = ohci->ed_controltail;
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if (!ohci->ed_controltail && !ohci->ed_rm_list) {
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wmb();
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ohci->hc_control |= OHCI_CTRL_CLE;
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ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
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ohci_writel (ohci, ohci->hc_control,
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&ohci->regs->control);
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}
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ohci->ed_controltail = ed;
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break;
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case PIPE_BULK:
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if (ohci->ed_bulktail == NULL) {
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WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
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ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
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} else {
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ohci->ed_bulktail->ed_next = ed;
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ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
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ed->dma);
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}
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ed->ed_prev = ohci->ed_bulktail;
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if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
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wmb();
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ohci->hc_control |= OHCI_CTRL_BLE;
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ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
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ohci_writel (ohci, ohci->hc_control,
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&ohci->regs->control);
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}
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ohci->ed_bulktail = ed;
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break;
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// case PIPE_INTERRUPT:
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// case PIPE_ISOCHRONOUS:
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default:
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branch = balance (ohci, ed->interval, ed->load);
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if (branch < 0) {
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ohci_dbg (ohci,
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"ERR %d, interval %d msecs, load %d\n",
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branch, ed->interval, ed->load);
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// FIXME if there are TDs queued, fail them!
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return branch;
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}
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ed->branch = branch;
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periodic_link (ohci, ed);
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}
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/* the HC may not see the schedule updates yet, but if it does
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* then they'll be properly ordered.
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*/
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return 0;
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}
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/*-------------------------------------------------------------------------*/
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/* scan the periodic table to find and unlink this ED */
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static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
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{
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int i;
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for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
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struct ed *temp;
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struct ed **prev = &ohci->periodic [i];
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__hc32 *prev_p = &ohci->hcca->int_table [i];
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while (*prev && (temp = *prev) != ed) {
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prev_p = &temp->hwNextED;
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prev = &temp->ed_next;
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}
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if (*prev) {
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*prev_p = ed->hwNextED;
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*prev = ed->ed_next;
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}
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ohci->load [i] -= ed->load;
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}
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ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
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ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
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(ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
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ed, ed->branch, ed->load, ed->interval);
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}
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/* unlink an ed from one of the HC chains.
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* just the link to the ed is unlinked.
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* the link from the ed still points to another operational ed or 0
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* so the HC can eventually finish the processing of the unlinked ed
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* (assuming it already started that, which needn't be true).
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*
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* ED_UNLINK is a transient state: the HC may still see this ED, but soon
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* it won't. ED_SKIP means the HC will finish its current transaction,
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* but won't start anything new. The TD queue may still grow; device
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* drivers don't know about this HCD-internal state.
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*
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* When the HC can't see the ED, something changes ED_UNLINK to one of:
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*
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* - ED_OPER: when there's any request queued, the ED gets rescheduled
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* immediately. HC should be working on them.
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*
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* - ED_IDLE: when there's no TD queue. there's no reason for the HC
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* to care about this ED; safe to disable the endpoint.
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*
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* When finish_unlinks() runs later, after SOF interrupt, it will often
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* complete one or more URB unlinks before making that state change.
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*/
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static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
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{
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ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
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wmb ();
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ed->state = ED_UNLINK;
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/* To deschedule something from the control or bulk list, just
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* clear CLE/BLE and wait. There's no safe way to scrub out list
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* head/current registers until later, and "later" isn't very
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* tightly specified. Figure 6-5 and Section 6.4.2.2 show how
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* the HC is reading the ED queues (while we modify them).
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*
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* For now, ed_schedule() is "later". It might be good paranoia
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* to scrub those registers in finish_unlinks(), in case of bugs
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* that make the HC try to use them.
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*/
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switch (ed->type) {
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case PIPE_CONTROL:
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/* remove ED from the HC's list: */
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if (ed->ed_prev == NULL) {
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if (!ed->hwNextED) {
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ohci->hc_control &= ~OHCI_CTRL_CLE;
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ohci_writel (ohci, ohci->hc_control,
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&ohci->regs->control);
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// a ohci_readl() later syncs CLE with the HC
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} else
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ohci_writel (ohci,
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hc32_to_cpup (ohci, &ed->hwNextED),
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&ohci->regs->ed_controlhead);
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} else {
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ed->ed_prev->ed_next = ed->ed_next;
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ed->ed_prev->hwNextED = ed->hwNextED;
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}
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/* remove ED from the HCD's list: */
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if (ohci->ed_controltail == ed) {
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ohci->ed_controltail = ed->ed_prev;
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if (ohci->ed_controltail)
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ohci->ed_controltail->ed_next = NULL;
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} else if (ed->ed_next) {
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ed->ed_next->ed_prev = ed->ed_prev;
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}
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break;
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case PIPE_BULK:
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/* remove ED from the HC's list: */
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if (ed->ed_prev == NULL) {
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if (!ed->hwNextED) {
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ohci->hc_control &= ~OHCI_CTRL_BLE;
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ohci_writel (ohci, ohci->hc_control,
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&ohci->regs->control);
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// a ohci_readl() later syncs BLE with the HC
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} else
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ohci_writel (ohci,
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hc32_to_cpup (ohci, &ed->hwNextED),
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&ohci->regs->ed_bulkhead);
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} else {
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ed->ed_prev->ed_next = ed->ed_next;
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ed->ed_prev->hwNextED = ed->hwNextED;
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}
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/* remove ED from the HCD's list: */
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if (ohci->ed_bulktail == ed) {
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ohci->ed_bulktail = ed->ed_prev;
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if (ohci->ed_bulktail)
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ohci->ed_bulktail->ed_next = NULL;
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} else if (ed->ed_next) {
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ed->ed_next->ed_prev = ed->ed_prev;
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}
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break;
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// case PIPE_INTERRUPT:
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// case PIPE_ISOCHRONOUS:
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default:
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periodic_unlink (ohci, ed);
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break;
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}
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}
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/*-------------------------------------------------------------------------*/
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/* get and maybe (re)init an endpoint. init _should_ be done only as part
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* of enumeration, usb_set_configuration() or usb_set_interface().
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*/
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static struct ed *ed_get (
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struct ohci_hcd *ohci,
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struct usb_host_endpoint *ep,
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struct usb_device *udev,
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unsigned int pipe,
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int interval
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) {
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struct ed *ed;
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unsigned long flags;
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spin_lock_irqsave (&ohci->lock, flags);
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if (!(ed = ep->hcpriv)) {
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struct td *td;
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int is_out;
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u32 info;
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ed = ed_alloc (ohci, GFP_ATOMIC);
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if (!ed) {
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/* out of memory */
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goto done;
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}
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/* dummy td; end of td list for ed */
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td = td_alloc (ohci, GFP_ATOMIC);
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if (!td) {
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/* out of memory */
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ed_free (ohci, ed);
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ed = NULL;
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goto done;
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}
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ed->dummy = td;
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ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
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ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
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ed->state = ED_IDLE;
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is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
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/* FIXME usbcore changes dev->devnum before SET_ADDRESS
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* suceeds ... otherwise we wouldn't need "pipe".
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*/
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info = usb_pipedevice (pipe);
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ed->type = usb_pipetype(pipe);
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info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
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info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
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if (udev->speed == USB_SPEED_LOW)
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info |= ED_LOWSPEED;
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/* only control transfers store pids in tds */
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if (ed->type != PIPE_CONTROL) {
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info |= is_out ? ED_OUT : ED_IN;
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if (ed->type != PIPE_BULK) {
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/* periodic transfers... */
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if (ed->type == PIPE_ISOCHRONOUS)
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info |= ED_ISO;
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else if (interval > 32) /* iso can be bigger */
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interval = 32;
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ed->interval = interval;
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ed->load = usb_calc_bus_time (
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udev->speed, !is_out,
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ed->type == PIPE_ISOCHRONOUS,
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le16_to_cpu(ep->desc.wMaxPacketSize))
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/ 1000;
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}
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}
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ed->hwINFO = cpu_to_hc32(ohci, info);
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ep->hcpriv = ed;
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}
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done:
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spin_unlock_irqrestore (&ohci->lock, flags);
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return ed;
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}
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|
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/*-------------------------------------------------------------------------*/
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/* request unlinking of an endpoint from an operational HC.
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* put the ep on the rm_list
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* real work is done at the next start frame (SF) hardware interrupt
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* caller guarantees HCD is running, so hardware access is safe,
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* and that ed->state is ED_OPER
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*/
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static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
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{
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ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
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ed_deschedule (ohci, ed);
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|
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/* rm_list is just singly linked, for simplicity */
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ed->ed_next = ohci->ed_rm_list;
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ed->ed_prev = NULL;
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ohci->ed_rm_list = ed;
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|
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/* enable SOF interrupt */
|
|
ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
|
|
ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
|
|
// flush those writes, and get latest HCCA contents
|
|
(void) ohci_readl (ohci, &ohci->regs->control);
|
|
|
|
/* SF interrupt might get delayed; record the frame counter value that
|
|
* indicates when the HC isn't looking at it, so concurrent unlinks
|
|
* behave. frame_no wraps every 2^16 msec, and changes right before
|
|
* SF is triggered.
|
|
*/
|
|
ed->tick = ohci_frame_no(ohci) + 1;
|
|
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*
|
|
* TD handling functions
|
|
*-------------------------------------------------------------------------*/
|
|
|
|
/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
|
|
|
|
static void
|
|
td_fill (struct ohci_hcd *ohci, u32 info,
|
|
dma_addr_t data, int len,
|
|
struct urb *urb, int index)
|
|
{
|
|
struct td *td, *td_pt;
|
|
struct urb_priv *urb_priv = urb->hcpriv;
|
|
int is_iso = info & TD_ISO;
|
|
int hash;
|
|
|
|
// ASSERT (index < urb_priv->length);
|
|
|
|
/* aim for only one interrupt per urb. mostly applies to control
|
|
* and iso; other urbs rarely need more than one TD per urb.
|
|
* this way, only final tds (or ones with an error) cause IRQs.
|
|
* at least immediately; use DI=6 in case any control request is
|
|
* tempted to die part way through. (and to force the hc to flush
|
|
* its donelist soonish, even on unlink paths.)
|
|
*
|
|
* NOTE: could delay interrupts even for the last TD, and get fewer
|
|
* interrupts ... increasing per-urb latency by sharing interrupts.
|
|
* Drivers that queue bulk urbs may request that behavior.
|
|
*/
|
|
if (index != (urb_priv->length - 1)
|
|
|| (urb->transfer_flags & URB_NO_INTERRUPT))
|
|
info |= TD_DI_SET (6);
|
|
|
|
/* use this td as the next dummy */
|
|
td_pt = urb_priv->td [index];
|
|
|
|
/* fill the old dummy TD */
|
|
td = urb_priv->td [index] = urb_priv->ed->dummy;
|
|
urb_priv->ed->dummy = td_pt;
|
|
|
|
td->ed = urb_priv->ed;
|
|
td->next_dl_td = NULL;
|
|
td->index = index;
|
|
td->urb = urb;
|
|
td->data_dma = data;
|
|
if (!len)
|
|
data = 0;
|
|
|
|
td->hwINFO = cpu_to_hc32 (ohci, info);
|
|
if (is_iso) {
|
|
td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
|
|
*ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
|
|
(data & 0x0FFF) | 0xE000);
|
|
td->ed->last_iso = info & 0xffff;
|
|
} else {
|
|
td->hwCBP = cpu_to_hc32 (ohci, data);
|
|
}
|
|
if (data)
|
|
td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
|
|
else
|
|
td->hwBE = 0;
|
|
td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
|
|
|
|
/* append to queue */
|
|
list_add_tail (&td->td_list, &td->ed->td_list);
|
|
|
|
/* hash it for later reverse mapping */
|
|
hash = TD_HASH_FUNC (td->td_dma);
|
|
td->td_hash = ohci->td_hash [hash];
|
|
ohci->td_hash [hash] = td;
|
|
|
|
/* HC might read the TD (or cachelines) right away ... */
|
|
wmb ();
|
|
td->ed->hwTailP = td->hwNextTD;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/* Prepare all TDs of a transfer, and queue them onto the ED.
|
|
* Caller guarantees HC is active.
|
|
* Usually the ED is already on the schedule, so TDs might be
|
|
* processed as soon as they're queued.
|
|
*/
|
|
static void td_submit_urb (
|
|
struct ohci_hcd *ohci,
|
|
struct urb *urb
|
|
) {
|
|
struct urb_priv *urb_priv = urb->hcpriv;
|
|
dma_addr_t data;
|
|
int data_len = urb->transfer_buffer_length;
|
|
int cnt = 0;
|
|
u32 info = 0;
|
|
int is_out = usb_pipeout (urb->pipe);
|
|
int periodic = 0;
|
|
|
|
/* OHCI handles the bulk/interrupt data toggles itself. We just
|
|
* use the device toggle bits for resetting, and rely on the fact
|
|
* that resetting toggle is meaningless if the endpoint is active.
|
|
*/
|
|
if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
|
|
usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
|
|
is_out, 1);
|
|
urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
|
|
}
|
|
|
|
urb_priv->td_cnt = 0;
|
|
list_add (&urb_priv->pending, &ohci->pending);
|
|
|
|
if (data_len)
|
|
data = urb->transfer_dma;
|
|
else
|
|
data = 0;
|
|
|
|
/* NOTE: TD_CC is set so we can tell which TDs the HC processed by
|
|
* using TD_CC_GET, as well as by seeing them on the done list.
|
|
* (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
|
|
*/
|
|
switch (urb_priv->ed->type) {
|
|
|
|
/* Bulk and interrupt are identical except for where in the schedule
|
|
* their EDs live.
|
|
*/
|
|
case PIPE_INTERRUPT:
|
|
/* ... and periodic urbs have extra accounting */
|
|
periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
|
|
&& ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
|
|
/* FALLTHROUGH */
|
|
case PIPE_BULK:
|
|
info = is_out
|
|
? TD_T_TOGGLE | TD_CC | TD_DP_OUT
|
|
: TD_T_TOGGLE | TD_CC | TD_DP_IN;
|
|
/* TDs _could_ transfer up to 8K each */
|
|
while (data_len > 4096) {
|
|
td_fill (ohci, info, data, 4096, urb, cnt);
|
|
data += 4096;
|
|
data_len -= 4096;
|
|
cnt++;
|
|
}
|
|
/* maybe avoid ED halt on final TD short read */
|
|
if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
|
|
info |= TD_R;
|
|
td_fill (ohci, info, data, data_len, urb, cnt);
|
|
cnt++;
|
|
if ((urb->transfer_flags & URB_ZERO_PACKET)
|
|
&& cnt < urb_priv->length) {
|
|
td_fill (ohci, info, 0, 0, urb, cnt);
|
|
cnt++;
|
|
}
|
|
/* maybe kickstart bulk list */
|
|
if (urb_priv->ed->type == PIPE_BULK) {
|
|
wmb ();
|
|
ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
|
|
}
|
|
break;
|
|
|
|
/* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
|
|
* any DATA phase works normally, and the STATUS ack is special.
|
|
*/
|
|
case PIPE_CONTROL:
|
|
info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
|
|
td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
|
|
if (data_len > 0) {
|
|
info = TD_CC | TD_R | TD_T_DATA1;
|
|
info |= is_out ? TD_DP_OUT : TD_DP_IN;
|
|
/* NOTE: mishandles transfers >8K, some >4K */
|
|
td_fill (ohci, info, data, data_len, urb, cnt++);
|
|
}
|
|
info = (is_out || data_len == 0)
|
|
? TD_CC | TD_DP_IN | TD_T_DATA1
|
|
: TD_CC | TD_DP_OUT | TD_T_DATA1;
|
|
td_fill (ohci, info, data, 0, urb, cnt++);
|
|
/* maybe kickstart control list */
|
|
wmb ();
|
|
ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
|
|
break;
|
|
|
|
/* ISO has no retransmit, so no toggle; and it uses special TDs.
|
|
* Each TD could handle multiple consecutive frames (interval 1);
|
|
* we could often reduce the number of TDs here.
|
|
*/
|
|
case PIPE_ISOCHRONOUS:
|
|
for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
|
|
int frame = urb->start_frame;
|
|
|
|
// FIXME scheduling should handle frame counter
|
|
// roll-around ... exotic case (and OHCI has
|
|
// a 2^16 iso range, vs other HCs max of 2^10)
|
|
frame += cnt * urb->interval;
|
|
frame &= 0xffff;
|
|
td_fill (ohci, TD_CC | TD_ISO | frame,
|
|
data + urb->iso_frame_desc [cnt].offset,
|
|
urb->iso_frame_desc [cnt].length, urb, cnt);
|
|
}
|
|
periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
|
|
&& ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
|
|
break;
|
|
}
|
|
|
|
/* start periodic dma if needed */
|
|
if (periodic) {
|
|
wmb ();
|
|
ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
|
|
ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
|
|
}
|
|
|
|
// ASSERT (urb_priv->length == cnt);
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*
|
|
* Done List handling functions
|
|
*-------------------------------------------------------------------------*/
|
|
|
|
/* calculate transfer length/status and update the urb
|
|
* PRECONDITION: irqsafe (only for urb->status locking)
|
|
*/
|
|
static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
|
|
{
|
|
u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
|
|
int cc = 0;
|
|
|
|
list_del (&td->td_list);
|
|
|
|
/* ISO ... drivers see per-TD length/status */
|
|
if (tdINFO & TD_ISO) {
|
|
u16 tdPSW = ohci_hwPSW (ohci, td, 0);
|
|
int dlen = 0;
|
|
|
|
/* NOTE: assumes FC in tdINFO == 0, and that
|
|
* only the first of 0..MAXPSW psws is used.
|
|
*/
|
|
|
|
cc = (tdPSW >> 12) & 0xF;
|
|
if (tdINFO & TD_CC) /* hc didn't touch? */
|
|
return;
|
|
|
|
if (usb_pipeout (urb->pipe))
|
|
dlen = urb->iso_frame_desc [td->index].length;
|
|
else {
|
|
/* short reads are always OK for ISO */
|
|
if (cc == TD_DATAUNDERRUN)
|
|
cc = TD_CC_NOERROR;
|
|
dlen = tdPSW & 0x3ff;
|
|
}
|
|
urb->actual_length += dlen;
|
|
urb->iso_frame_desc [td->index].actual_length = dlen;
|
|
urb->iso_frame_desc [td->index].status = cc_to_error [cc];
|
|
|
|
if (cc != TD_CC_NOERROR)
|
|
ohci_vdbg (ohci,
|
|
"urb %p iso td %p (%d) len %d cc %d\n",
|
|
urb, td, 1 + td->index, dlen, cc);
|
|
|
|
/* BULK, INT, CONTROL ... drivers see aggregate length/status,
|
|
* except that "setup" bytes aren't counted and "short" transfers
|
|
* might not be reported as errors.
|
|
*/
|
|
} else {
|
|
int type = usb_pipetype (urb->pipe);
|
|
u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
|
|
|
|
cc = TD_CC_GET (tdINFO);
|
|
|
|
/* update packet status if needed (short is normally ok) */
|
|
if (cc == TD_DATAUNDERRUN
|
|
&& !(urb->transfer_flags & URB_SHORT_NOT_OK))
|
|
cc = TD_CC_NOERROR;
|
|
if (cc != TD_CC_NOERROR && cc < 0x0E) {
|
|
spin_lock (&urb->lock);
|
|
if (urb->status == -EINPROGRESS)
|
|
urb->status = cc_to_error [cc];
|
|
spin_unlock (&urb->lock);
|
|
}
|
|
|
|
/* count all non-empty packets except control SETUP packet */
|
|
if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
|
|
if (td->hwCBP == 0)
|
|
urb->actual_length += tdBE - td->data_dma + 1;
|
|
else
|
|
urb->actual_length +=
|
|
hc32_to_cpup (ohci, &td->hwCBP)
|
|
- td->data_dma;
|
|
}
|
|
|
|
if (cc != TD_CC_NOERROR && cc < 0x0E)
|
|
ohci_vdbg (ohci,
|
|
"urb %p td %p (%d) cc %d, len=%d/%d\n",
|
|
urb, td, 1 + td->index, cc,
|
|
urb->actual_length,
|
|
urb->transfer_buffer_length);
|
|
}
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static inline struct td *
|
|
ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
|
|
{
|
|
struct urb *urb = td->urb;
|
|
struct ed *ed = td->ed;
|
|
struct list_head *tmp = td->td_list.next;
|
|
__hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
|
|
|
|
/* clear ed halt; this is the td that caused it, but keep it inactive
|
|
* until its urb->complete() has a chance to clean up.
|
|
*/
|
|
ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
|
|
wmb ();
|
|
ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
|
|
|
|
/* put any later tds from this urb onto the donelist, after 'td',
|
|
* order won't matter here: no errors, and nothing was transferred.
|
|
* also patch the ed so it looks as if those tds completed normally.
|
|
*/
|
|
while (tmp != &ed->td_list) {
|
|
struct td *next;
|
|
__hc32 info;
|
|
|
|
next = list_entry (tmp, struct td, td_list);
|
|
tmp = next->td_list.next;
|
|
|
|
if (next->urb != urb)
|
|
break;
|
|
|
|
/* NOTE: if multi-td control DATA segments get supported,
|
|
* this urb had one of them, this td wasn't the last td
|
|
* in that segment (TD_R clear), this ed halted because
|
|
* of a short read, _and_ URB_SHORT_NOT_OK is clear ...
|
|
* then we need to leave the control STATUS packet queued
|
|
* and clear ED_SKIP.
|
|
*/
|
|
info = next->hwINFO;
|
|
info |= cpu_to_hc32 (ohci, TD_DONE);
|
|
info &= ~cpu_to_hc32 (ohci, TD_CC);
|
|
next->hwINFO = info;
|
|
|
|
next->next_dl_td = rev;
|
|
rev = next;
|
|
|
|
ed->hwHeadP = next->hwNextTD | toggle;
|
|
}
|
|
|
|
/* help for troubleshooting: report anything that
|
|
* looks odd ... that doesn't include protocol stalls
|
|
* (or maybe some other things)
|
|
*/
|
|
switch (cc) {
|
|
case TD_DATAUNDERRUN:
|
|
if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
|
|
break;
|
|
/* fallthrough */
|
|
case TD_CC_STALL:
|
|
if (usb_pipecontrol (urb->pipe))
|
|
break;
|
|
/* fallthrough */
|
|
default:
|
|
ohci_dbg (ohci,
|
|
"urb %p path %s ep%d%s %08x cc %d --> status %d\n",
|
|
urb, urb->dev->devpath,
|
|
usb_pipeendpoint (urb->pipe),
|
|
usb_pipein (urb->pipe) ? "in" : "out",
|
|
hc32_to_cpu (ohci, td->hwINFO),
|
|
cc, cc_to_error [cc]);
|
|
}
|
|
|
|
return rev;
|
|
}
|
|
|
|
/* replies to the request have to be on a FIFO basis so
|
|
* we unreverse the hc-reversed done-list
|
|
*/
|
|
static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
|
|
{
|
|
u32 td_dma;
|
|
struct td *td_rev = NULL;
|
|
struct td *td = NULL;
|
|
|
|
td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
|
|
ohci->hcca->done_head = 0;
|
|
wmb();
|
|
|
|
/* get TD from hc's singly linked list, and
|
|
* prepend to ours. ed->td_list changes later.
|
|
*/
|
|
while (td_dma) {
|
|
int cc;
|
|
|
|
td = dma_to_td (ohci, td_dma);
|
|
if (!td) {
|
|
ohci_err (ohci, "bad entry %8x\n", td_dma);
|
|
break;
|
|
}
|
|
|
|
td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
|
|
cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
|
|
|
|
/* Non-iso endpoints can halt on error; un-halt,
|
|
* and dequeue any other TDs from this urb.
|
|
* No other TD could have caused the halt.
|
|
*/
|
|
if (cc != TD_CC_NOERROR
|
|
&& (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
|
|
td_rev = ed_halted (ohci, td, cc, td_rev);
|
|
|
|
td->next_dl_td = td_rev;
|
|
td_rev = td;
|
|
td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
|
|
}
|
|
return td_rev;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
|
|
static void
|
|
finish_unlinks (struct ohci_hcd *ohci, u16 tick, struct pt_regs *regs)
|
|
{
|
|
struct ed *ed, **last;
|
|
|
|
rescan_all:
|
|
for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
|
|
struct list_head *entry, *tmp;
|
|
int completed, modified;
|
|
__hc32 *prev;
|
|
|
|
/* only take off EDs that the HC isn't using, accounting for
|
|
* frame counter wraps and EDs with partially retired TDs
|
|
*/
|
|
if (likely (regs && HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
|
|
if (tick_before (tick, ed->tick)) {
|
|
skip_ed:
|
|
last = &ed->ed_next;
|
|
continue;
|
|
}
|
|
|
|
if (!list_empty (&ed->td_list)) {
|
|
struct td *td;
|
|
u32 head;
|
|
|
|
td = list_entry (ed->td_list.next, struct td,
|
|
td_list);
|
|
head = hc32_to_cpu (ohci, ed->hwHeadP) &
|
|
TD_MASK;
|
|
|
|
/* INTR_WDH may need to clean up first */
|
|
if (td->td_dma != head)
|
|
goto skip_ed;
|
|
}
|
|
}
|
|
|
|
/* reentrancy: if we drop the schedule lock, someone might
|
|
* have modified this list. normally it's just prepending
|
|
* entries (which we'd ignore), but paranoia won't hurt.
|
|
*/
|
|
*last = ed->ed_next;
|
|
ed->ed_next = NULL;
|
|
modified = 0;
|
|
|
|
/* unlink urbs as requested, but rescan the list after
|
|
* we call a completion since it might have unlinked
|
|
* another (earlier) urb
|
|
*
|
|
* When we get here, the HC doesn't see this ed. But it
|
|
* must not be rescheduled until all completed URBs have
|
|
* been given back to the driver.
|
|
*/
|
|
rescan_this:
|
|
completed = 0;
|
|
prev = &ed->hwHeadP;
|
|
list_for_each_safe (entry, tmp, &ed->td_list) {
|
|
struct td *td;
|
|
struct urb *urb;
|
|
urb_priv_t *urb_priv;
|
|
__hc32 savebits;
|
|
|
|
td = list_entry (entry, struct td, td_list);
|
|
urb = td->urb;
|
|
urb_priv = td->urb->hcpriv;
|
|
|
|
if (urb->status == -EINPROGRESS) {
|
|
prev = &td->hwNextTD;
|
|
continue;
|
|
}
|
|
|
|
/* patch pointer hc uses */
|
|
savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
|
|
*prev = td->hwNextTD | savebits;
|
|
|
|
/* HC may have partly processed this TD */
|
|
td_done (ohci, urb, td);
|
|
urb_priv->td_cnt++;
|
|
|
|
/* if URB is done, clean up */
|
|
if (urb_priv->td_cnt == urb_priv->length) {
|
|
modified = completed = 1;
|
|
finish_urb (ohci, urb, regs);
|
|
}
|
|
}
|
|
if (completed && !list_empty (&ed->td_list))
|
|
goto rescan_this;
|
|
|
|
/* ED's now officially unlinked, hc doesn't see */
|
|
ed->state = ED_IDLE;
|
|
ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
|
|
ed->hwNextED = 0;
|
|
wmb ();
|
|
ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
|
|
|
|
/* but if there's work queued, reschedule */
|
|
if (!list_empty (&ed->td_list)) {
|
|
if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))
|
|
ed_schedule (ohci, ed);
|
|
}
|
|
|
|
if (modified)
|
|
goto rescan_all;
|
|
}
|
|
|
|
/* maybe reenable control and bulk lists */
|
|
if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
|
|
&& ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
|
|
&& !ohci->ed_rm_list) {
|
|
u32 command = 0, control = 0;
|
|
|
|
if (ohci->ed_controltail) {
|
|
command |= OHCI_CLF;
|
|
if (ohci->flags & OHCI_QUIRK_ZFMICRO)
|
|
mdelay(1);
|
|
if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
|
|
control |= OHCI_CTRL_CLE;
|
|
ohci_writel (ohci, 0,
|
|
&ohci->regs->ed_controlcurrent);
|
|
}
|
|
}
|
|
if (ohci->ed_bulktail) {
|
|
command |= OHCI_BLF;
|
|
if (ohci->flags & OHCI_QUIRK_ZFMICRO)
|
|
mdelay(1);
|
|
if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
|
|
control |= OHCI_CTRL_BLE;
|
|
ohci_writel (ohci, 0,
|
|
&ohci->regs->ed_bulkcurrent);
|
|
}
|
|
}
|
|
|
|
/* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
|
|
if (control) {
|
|
ohci->hc_control |= control;
|
|
if (ohci->flags & OHCI_QUIRK_ZFMICRO)
|
|
mdelay(1);
|
|
ohci_writel (ohci, ohci->hc_control,
|
|
&ohci->regs->control);
|
|
}
|
|
if (command) {
|
|
if (ohci->flags & OHCI_QUIRK_ZFMICRO)
|
|
mdelay(1);
|
|
ohci_writel (ohci, command, &ohci->regs->cmdstatus);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* Process normal completions (error or success) and clean the schedules.
|
|
*
|
|
* This is the main path for handing urbs back to drivers. The only other
|
|
* path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
|
|
* scanning the (re-reversed) donelist as this does.
|
|
*/
|
|
static void
|
|
dl_done_list (struct ohci_hcd *ohci, struct pt_regs *regs)
|
|
{
|
|
struct td *td = dl_reverse_done_list (ohci);
|
|
|
|
while (td) {
|
|
struct td *td_next = td->next_dl_td;
|
|
struct urb *urb = td->urb;
|
|
urb_priv_t *urb_priv = urb->hcpriv;
|
|
struct ed *ed = td->ed;
|
|
|
|
/* update URB's length and status from TD */
|
|
td_done (ohci, urb, td);
|
|
urb_priv->td_cnt++;
|
|
|
|
/* If all this urb's TDs are done, call complete() */
|
|
if (urb_priv->td_cnt == urb_priv->length)
|
|
finish_urb (ohci, urb, regs);
|
|
|
|
/* clean schedule: unlink EDs that are no longer busy */
|
|
if (list_empty (&ed->td_list)) {
|
|
if (ed->state == ED_OPER)
|
|
start_ed_unlink (ohci, ed);
|
|
|
|
/* ... reenabling halted EDs only after fault cleanup */
|
|
} else if ((ed->hwINFO & cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE))
|
|
== cpu_to_hc32 (ohci, ED_SKIP)) {
|
|
td = list_entry (ed->td_list.next, struct td, td_list);
|
|
if (!(td->hwINFO & cpu_to_hc32 (ohci, TD_DONE))) {
|
|
ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP);
|
|
/* ... hc may need waking-up */
|
|
switch (ed->type) {
|
|
case PIPE_CONTROL:
|
|
ohci_writel (ohci, OHCI_CLF,
|
|
&ohci->regs->cmdstatus);
|
|
break;
|
|
case PIPE_BULK:
|
|
ohci_writel (ohci, OHCI_BLF,
|
|
&ohci->regs->cmdstatus);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
td = td_next;
|
|
}
|
|
}
|