![Jörn Engel](/assets/img/avatar_default.png)
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
943 lines
25 KiB
C
943 lines
25 KiB
C
/*
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* Universal Host Controller Interface driver for USB.
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*
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* Maintainer: Alan Stern <stern@rowland.harvard.edu>
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*
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* (C) Copyright 1999 Linus Torvalds
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* (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
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* (C) Copyright 1999 Randy Dunlap
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* (C) Copyright 1999 Georg Acher, acher@in.tum.de
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* (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
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* (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
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* (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
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* (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
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* support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
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* (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
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* (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu
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*
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* Intel documents this fairly well, and as far as I know there
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* are no royalties or anything like that, but even so there are
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* people who decided that they want to do the same thing in a
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* completely different way.
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*
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/debugfs.h>
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#include <linux/pm.h>
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#include <linux/dmapool.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb.h>
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#include <linux/bitops.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include "../core/hcd.h"
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#include "uhci-hcd.h"
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#include "pci-quirks.h"
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/*
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* Version Information
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*/
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#define DRIVER_VERSION "v3.0"
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#define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
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Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
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Alan Stern"
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#define DRIVER_DESC "USB Universal Host Controller Interface driver"
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/*
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* debug = 0, no debugging messages
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* debug = 1, dump failed URBs except for stalls
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* debug = 2, dump all failed URBs (including stalls)
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* show all queues in /debug/uhci/[pci_addr]
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* debug = 3, show all TDs in URBs when dumping
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*/
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#ifdef DEBUG
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#define DEBUG_CONFIGURED 1
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static int debug = 1;
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module_param(debug, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(debug, "Debug level");
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#else
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#define DEBUG_CONFIGURED 0
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#define debug 0
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#endif
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static char *errbuf;
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#define ERRBUF_LEN (32 * 1024)
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static kmem_cache_t *uhci_up_cachep; /* urb_priv */
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static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state);
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static void wakeup_rh(struct uhci_hcd *uhci);
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static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
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#include "uhci-debug.c"
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#include "uhci-q.c"
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#include "uhci-hub.c"
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/*
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* Finish up a host controller reset and update the recorded state.
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*/
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static void finish_reset(struct uhci_hcd *uhci)
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{
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int port;
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/* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
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* bits in the port status and control registers.
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* We have to clear them by hand.
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*/
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for (port = 0; port < uhci->rh_numports; ++port)
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outw(0, uhci->io_addr + USBPORTSC1 + (port * 2));
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uhci->port_c_suspend = uhci->resuming_ports = 0;
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uhci->rh_state = UHCI_RH_RESET;
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uhci->is_stopped = UHCI_IS_STOPPED;
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uhci_to_hcd(uhci)->state = HC_STATE_HALT;
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uhci_to_hcd(uhci)->poll_rh = 0;
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uhci->dead = 0; /* Full reset resurrects the controller */
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}
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/*
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* Last rites for a defunct/nonfunctional controller
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* or one we don't want to use any more.
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*/
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static void uhci_hc_died(struct uhci_hcd *uhci)
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{
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uhci_get_current_frame_number(uhci);
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uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr);
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finish_reset(uhci);
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uhci->dead = 1;
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/* The current frame may already be partway finished */
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++uhci->frame_number;
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}
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/*
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* Initialize a controller that was newly discovered or has lost power
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* or otherwise been reset while it was suspended. In none of these cases
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* can we be sure of its previous state.
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*/
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static void check_and_reset_hc(struct uhci_hcd *uhci)
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{
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if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr))
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finish_reset(uhci);
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}
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/*
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* Store the basic register settings needed by the controller.
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*/
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static void configure_hc(struct uhci_hcd *uhci)
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{
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/* Set the frame length to the default: 1 ms exactly */
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outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF);
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/* Store the frame list base address */
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outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD);
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/* Set the current frame number */
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outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER,
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uhci->io_addr + USBFRNUM);
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/* Mark controller as not halted before we enable interrupts */
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uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED;
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mb();
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/* Enable PIRQ */
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pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
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USBLEGSUP_DEFAULT);
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}
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static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
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{
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int port;
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switch (to_pci_dev(uhci_dev(uhci))->vendor) {
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default:
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break;
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case PCI_VENDOR_ID_GENESYS:
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/* Genesys Logic's GL880S controllers don't generate
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* resume-detect interrupts.
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*/
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return 1;
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case PCI_VENDOR_ID_INTEL:
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/* Some of Intel's USB controllers have a bug that causes
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* resume-detect interrupts if any port has an over-current
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* condition. To make matters worse, some motherboards
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* hardwire unused USB ports' over-current inputs active!
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* To prevent problems, we will not enable resume-detect
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* interrupts if any ports are OC.
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*/
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for (port = 0; port < uhci->rh_numports; ++port) {
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if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
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USBPORTSC_OC)
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return 1;
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}
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break;
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}
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return 0;
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}
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static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
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__releases(uhci->lock)
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__acquires(uhci->lock)
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{
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int auto_stop;
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int int_enable;
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auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
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dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev,
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"%s%s\n", __FUNCTION__,
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(auto_stop ? " (auto-stop)" : ""));
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/* If we get a suspend request when we're already auto-stopped
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* then there's nothing to do.
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*/
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if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) {
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uhci->rh_state = new_state;
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return;
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}
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/* Enable resume-detect interrupts if they work.
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* Then enter Global Suspend mode, still configured.
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*/
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uhci->working_RD = 1;
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int_enable = USBINTR_RESUME;
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if (resume_detect_interrupts_are_broken(uhci)) {
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uhci->working_RD = int_enable = 0;
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}
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outw(int_enable, uhci->io_addr + USBINTR);
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outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD);
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mb();
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udelay(5);
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/* If we're auto-stopping then no devices have been attached
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* for a while, so there shouldn't be any active URBs and the
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* controller should stop after a few microseconds. Otherwise
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* we will give the controller one frame to stop.
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*/
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if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) {
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uhci->rh_state = UHCI_RH_SUSPENDING;
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spin_unlock_irq(&uhci->lock);
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msleep(1);
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spin_lock_irq(&uhci->lock);
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if (uhci->dead)
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return;
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}
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if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH))
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dev_warn(&uhci_to_hcd(uhci)->self.root_hub->dev,
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"Controller not stopped yet!\n");
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uhci_get_current_frame_number(uhci);
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uhci->rh_state = new_state;
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uhci->is_stopped = UHCI_IS_STOPPED;
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uhci_to_hcd(uhci)->poll_rh = !int_enable;
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uhci_scan_schedule(uhci, NULL);
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uhci_fsbr_off(uhci);
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}
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static void start_rh(struct uhci_hcd *uhci)
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{
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uhci_to_hcd(uhci)->state = HC_STATE_RUNNING;
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uhci->is_stopped = 0;
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/* Mark it configured and running with a 64-byte max packet.
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* All interrupts are enabled, even though RESUME won't do anything.
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*/
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outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD);
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outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
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uhci->io_addr + USBINTR);
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mb();
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uhci->rh_state = UHCI_RH_RUNNING;
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uhci_to_hcd(uhci)->poll_rh = 1;
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}
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static void wakeup_rh(struct uhci_hcd *uhci)
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__releases(uhci->lock)
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__acquires(uhci->lock)
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{
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dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev,
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"%s%s\n", __FUNCTION__,
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uhci->rh_state == UHCI_RH_AUTO_STOPPED ?
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" (auto-start)" : "");
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/* If we are auto-stopped then no devices are attached so there's
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* no need for wakeup signals. Otherwise we send Global Resume
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* for 20 ms.
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*/
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if (uhci->rh_state == UHCI_RH_SUSPENDED) {
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uhci->rh_state = UHCI_RH_RESUMING;
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outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF,
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uhci->io_addr + USBCMD);
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spin_unlock_irq(&uhci->lock);
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msleep(20);
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spin_lock_irq(&uhci->lock);
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if (uhci->dead)
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return;
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/* End Global Resume and wait for EOP to be sent */
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outw(USBCMD_CF, uhci->io_addr + USBCMD);
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mb();
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udelay(4);
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if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR)
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dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
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}
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start_rh(uhci);
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/* Restart root hub polling */
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mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
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}
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static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs)
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{
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struct uhci_hcd *uhci = hcd_to_uhci(hcd);
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unsigned short status;
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unsigned long flags;
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/*
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* Read the interrupt status, and write it back to clear the
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* interrupt cause. Contrary to the UHCI specification, the
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* "HC Halted" status bit is persistent: it is RO, not R/WC.
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*/
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status = inw(uhci->io_addr + USBSTS);
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if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
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return IRQ_NONE;
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outw(status, uhci->io_addr + USBSTS); /* Clear it */
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if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
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if (status & USBSTS_HSE)
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dev_err(uhci_dev(uhci), "host system error, "
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"PCI problems?\n");
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if (status & USBSTS_HCPE)
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dev_err(uhci_dev(uhci), "host controller process "
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"error, something bad happened!\n");
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if (status & USBSTS_HCH) {
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spin_lock_irqsave(&uhci->lock, flags);
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if (uhci->rh_state >= UHCI_RH_RUNNING) {
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dev_err(uhci_dev(uhci),
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"host controller halted, "
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"very bad!\n");
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if (debug > 1 && errbuf) {
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/* Print the schedule for debugging */
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uhci_sprint_schedule(uhci,
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errbuf, ERRBUF_LEN);
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lprintk(errbuf);
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}
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uhci_hc_died(uhci);
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/* Force a callback in case there are
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* pending unlinks */
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mod_timer(&hcd->rh_timer, jiffies);
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}
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spin_unlock_irqrestore(&uhci->lock, flags);
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}
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}
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if (status & USBSTS_RD)
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usb_hcd_poll_rh_status(hcd);
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else {
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spin_lock_irqsave(&uhci->lock, flags);
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uhci_scan_schedule(uhci, regs);
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spin_unlock_irqrestore(&uhci->lock, flags);
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}
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return IRQ_HANDLED;
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}
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/*
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* Store the current frame number in uhci->frame_number if the controller
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* is runnning. Expand from 11 bits (of which we use only 10) to a
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* full-sized integer.
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*
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* Like many other parts of the driver, this code relies on being polled
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* more than once per second as long as the controller is running.
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*/
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static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
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{
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if (!uhci->is_stopped) {
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unsigned delta;
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delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) &
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(UHCI_NUMFRAMES - 1);
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uhci->frame_number += delta;
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}
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}
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/*
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* De-allocate all resources
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*/
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static void release_uhci(struct uhci_hcd *uhci)
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{
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int i;
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if (DEBUG_CONFIGURED) {
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spin_lock_irq(&uhci->lock);
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uhci->is_initialized = 0;
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spin_unlock_irq(&uhci->lock);
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debugfs_remove(uhci->dentry);
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}
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for (i = 0; i < UHCI_NUM_SKELQH; i++)
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uhci_free_qh(uhci, uhci->skelqh[i]);
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uhci_free_td(uhci, uhci->term_td);
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dma_pool_destroy(uhci->qh_pool);
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dma_pool_destroy(uhci->td_pool);
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kfree(uhci->frame_cpu);
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dma_free_coherent(uhci_dev(uhci),
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UHCI_NUMFRAMES * sizeof(*uhci->frame),
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uhci->frame, uhci->frame_dma_handle);
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}
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static int uhci_init(struct usb_hcd *hcd)
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{
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struct uhci_hcd *uhci = hcd_to_uhci(hcd);
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unsigned io_size = (unsigned) hcd->rsrc_len;
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int port;
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uhci->io_addr = (unsigned long) hcd->rsrc_start;
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/* The UHCI spec says devices must have 2 ports, and goes on to say
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* they may have more but gives no way to determine how many there
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* are. However according to the UHCI spec, Bit 7 of the port
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* status and control register is always set to 1. So we try to
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* use this to our advantage. Another common failure mode when
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* a nonexistent register is addressed is to return all ones, so
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* we test for that also.
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*/
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for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
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unsigned int portstatus;
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portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2));
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if (!(portstatus & 0x0080) || portstatus == 0xffff)
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break;
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}
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if (debug)
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dev_info(uhci_dev(uhci), "detected %d ports\n", port);
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/* Anything greater than 7 is weird so we'll ignore it. */
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if (port > UHCI_RH_MAXCHILD) {
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dev_info(uhci_dev(uhci), "port count misdetected? "
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"forcing to 2 ports\n");
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port = 2;
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}
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uhci->rh_numports = port;
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/* Kick BIOS off this hardware and reset if the controller
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* isn't already safely quiescent.
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*/
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check_and_reset_hc(uhci);
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return 0;
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}
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/* Make sure the controller is quiescent and that we're not using it
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* any more. This is mainly for the benefit of programs which, like kexec,
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* expect the hardware to be idle: not doing DMA or generating IRQs.
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*
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* This routine may be called in a damaged or failing kernel. Hence we
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* do not acquire the spinlock before shutting down the controller.
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*/
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static void uhci_shutdown(struct pci_dev *pdev)
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{
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struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev);
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uhci_hc_died(hcd_to_uhci(hcd));
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}
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/*
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* Allocate a frame list, and then setup the skeleton
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*
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* The hardware doesn't really know any difference
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* in the queues, but the order does matter for the
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* protocols higher up. The order is:
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*
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* - any isochronous events handled before any
|
|
* of the queues. We don't do that here, because
|
|
* we'll create the actual TD entries on demand.
|
|
* - The first queue is the interrupt queue.
|
|
* - The second queue is the control queue, split into low- and full-speed
|
|
* - The third queue is bulk queue.
|
|
* - The fourth queue is the bandwidth reclamation queue, which loops back
|
|
* to the full-speed control queue.
|
|
*/
|
|
static int uhci_start(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
int retval = -EBUSY;
|
|
int i;
|
|
struct dentry *dentry;
|
|
|
|
hcd->uses_new_polling = 1;
|
|
|
|
spin_lock_init(&uhci->lock);
|
|
setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout,
|
|
(unsigned long) uhci);
|
|
INIT_LIST_HEAD(&uhci->idle_qh_list);
|
|
init_waitqueue_head(&uhci->waitqh);
|
|
|
|
if (DEBUG_CONFIGURED) {
|
|
dentry = debugfs_create_file(hcd->self.bus_name,
|
|
S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root,
|
|
uhci, &uhci_debug_operations);
|
|
if (!dentry) {
|
|
dev_err(uhci_dev(uhci), "couldn't create uhci "
|
|
"debugfs entry\n");
|
|
retval = -ENOMEM;
|
|
goto err_create_debug_entry;
|
|
}
|
|
uhci->dentry = dentry;
|
|
}
|
|
|
|
uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
|
|
UHCI_NUMFRAMES * sizeof(*uhci->frame),
|
|
&uhci->frame_dma_handle, 0);
|
|
if (!uhci->frame) {
|
|
dev_err(uhci_dev(uhci), "unable to allocate "
|
|
"consistent memory for frame list\n");
|
|
goto err_alloc_frame;
|
|
}
|
|
memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame));
|
|
|
|
uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
|
|
GFP_KERNEL);
|
|
if (!uhci->frame_cpu) {
|
|
dev_err(uhci_dev(uhci), "unable to allocate "
|
|
"memory for frame pointers\n");
|
|
goto err_alloc_frame_cpu;
|
|
}
|
|
|
|
uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
|
|
sizeof(struct uhci_td), 16, 0);
|
|
if (!uhci->td_pool) {
|
|
dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
|
|
goto err_create_td_pool;
|
|
}
|
|
|
|
uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
|
|
sizeof(struct uhci_qh), 16, 0);
|
|
if (!uhci->qh_pool) {
|
|
dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
|
|
goto err_create_qh_pool;
|
|
}
|
|
|
|
uhci->term_td = uhci_alloc_td(uhci);
|
|
if (!uhci->term_td) {
|
|
dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
|
|
goto err_alloc_term_td;
|
|
}
|
|
|
|
for (i = 0; i < UHCI_NUM_SKELQH; i++) {
|
|
uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL);
|
|
if (!uhci->skelqh[i]) {
|
|
dev_err(uhci_dev(uhci), "unable to allocate QH\n");
|
|
goto err_alloc_skelqh;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* 8 Interrupt queues; link all higher int queues to int1,
|
|
* then link int1 to control and control to bulk
|
|
*/
|
|
uhci->skel_int128_qh->link =
|
|
uhci->skel_int64_qh->link =
|
|
uhci->skel_int32_qh->link =
|
|
uhci->skel_int16_qh->link =
|
|
uhci->skel_int8_qh->link =
|
|
uhci->skel_int4_qh->link =
|
|
uhci->skel_int2_qh->link = UHCI_PTR_QH |
|
|
cpu_to_le32(uhci->skel_int1_qh->dma_handle);
|
|
|
|
uhci->skel_int1_qh->link = UHCI_PTR_QH |
|
|
cpu_to_le32(uhci->skel_ls_control_qh->dma_handle);
|
|
uhci->skel_ls_control_qh->link = UHCI_PTR_QH |
|
|
cpu_to_le32(uhci->skel_fs_control_qh->dma_handle);
|
|
uhci->skel_fs_control_qh->link = UHCI_PTR_QH |
|
|
cpu_to_le32(uhci->skel_bulk_qh->dma_handle);
|
|
uhci->skel_bulk_qh->link = UHCI_PTR_QH |
|
|
cpu_to_le32(uhci->skel_term_qh->dma_handle);
|
|
|
|
/* This dummy TD is to work around a bug in Intel PIIX controllers */
|
|
uhci_fill_td(uhci->term_td, 0, uhci_explen(0) |
|
|
(0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
|
|
uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);
|
|
|
|
uhci->skel_term_qh->link = UHCI_PTR_TERM;
|
|
uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);
|
|
|
|
/*
|
|
* Fill the frame list: make all entries point to the proper
|
|
* interrupt queue.
|
|
*
|
|
* The interrupt queues will be interleaved as evenly as possible.
|
|
* There's not much to be done about period-1 interrupts; they have
|
|
* to occur in every frame. But we can schedule period-2 interrupts
|
|
* in odd-numbered frames, period-4 interrupts in frames congruent
|
|
* to 2 (mod 4), and so on. This way each frame only has two
|
|
* interrupt QHs, which will help spread out bandwidth utilization.
|
|
*/
|
|
for (i = 0; i < UHCI_NUMFRAMES; i++) {
|
|
int irq;
|
|
|
|
/*
|
|
* ffs (Find First bit Set) does exactly what we need:
|
|
* 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[8],
|
|
* 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[7], etc.
|
|
* ffs >= 7 => not on any high-period queue, so use
|
|
* skel_int1_qh = skelqh[9].
|
|
* Add UHCI_NUMFRAMES to insure at least one bit is set.
|
|
*/
|
|
irq = 8 - (int) __ffs(i + UHCI_NUMFRAMES);
|
|
if (irq <= 1)
|
|
irq = 9;
|
|
|
|
/* Only place we don't use the frame list routines */
|
|
uhci->frame[i] = UHCI_PTR_QH |
|
|
cpu_to_le32(uhci->skelqh[irq]->dma_handle);
|
|
}
|
|
|
|
/*
|
|
* Some architectures require a full mb() to enforce completion of
|
|
* the memory writes above before the I/O transfers in configure_hc().
|
|
*/
|
|
mb();
|
|
|
|
configure_hc(uhci);
|
|
uhci->is_initialized = 1;
|
|
start_rh(uhci);
|
|
return 0;
|
|
|
|
/*
|
|
* error exits:
|
|
*/
|
|
err_alloc_skelqh:
|
|
for (i = 0; i < UHCI_NUM_SKELQH; i++) {
|
|
if (uhci->skelqh[i])
|
|
uhci_free_qh(uhci, uhci->skelqh[i]);
|
|
}
|
|
|
|
uhci_free_td(uhci, uhci->term_td);
|
|
|
|
err_alloc_term_td:
|
|
dma_pool_destroy(uhci->qh_pool);
|
|
|
|
err_create_qh_pool:
|
|
dma_pool_destroy(uhci->td_pool);
|
|
|
|
err_create_td_pool:
|
|
kfree(uhci->frame_cpu);
|
|
|
|
err_alloc_frame_cpu:
|
|
dma_free_coherent(uhci_dev(uhci),
|
|
UHCI_NUMFRAMES * sizeof(*uhci->frame),
|
|
uhci->frame, uhci->frame_dma_handle);
|
|
|
|
err_alloc_frame:
|
|
debugfs_remove(uhci->dentry);
|
|
|
|
err_create_debug_entry:
|
|
return retval;
|
|
}
|
|
|
|
static void uhci_stop(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && !uhci->dead)
|
|
uhci_hc_died(uhci);
|
|
uhci_scan_schedule(uhci, NULL);
|
|
spin_unlock_irq(&uhci->lock);
|
|
|
|
del_timer_sync(&uhci->fsbr_timer);
|
|
release_uhci(uhci);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int uhci_rh_suspend(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
int rc = 0;
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
|
|
rc = -ESHUTDOWN;
|
|
else if (!uhci->dead)
|
|
suspend_rh(uhci, UHCI_RH_SUSPENDED);
|
|
spin_unlock_irq(&uhci->lock);
|
|
return rc;
|
|
}
|
|
|
|
static int uhci_rh_resume(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
int rc = 0;
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
|
|
dev_warn(&hcd->self.root_hub->dev, "HC isn't running!\n");
|
|
rc = -ESHUTDOWN;
|
|
} else if (!uhci->dead)
|
|
wakeup_rh(uhci);
|
|
spin_unlock_irq(&uhci->lock);
|
|
return rc;
|
|
}
|
|
|
|
static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
int rc = 0;
|
|
|
|
dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) || uhci->dead)
|
|
goto done_okay; /* Already suspended or dead */
|
|
|
|
if (uhci->rh_state > UHCI_RH_SUSPENDED) {
|
|
dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n");
|
|
rc = -EBUSY;
|
|
goto done;
|
|
};
|
|
|
|
/* All PCI host controllers are required to disable IRQ generation
|
|
* at the source, so we must turn off PIRQ.
|
|
*/
|
|
pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
|
|
mb();
|
|
hcd->poll_rh = 0;
|
|
|
|
/* FIXME: Enable non-PME# remote wakeup? */
|
|
|
|
done_okay:
|
|
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
|
done:
|
|
spin_unlock_irq(&uhci->lock);
|
|
return rc;
|
|
}
|
|
|
|
static int uhci_resume(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
|
|
dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
|
|
|
|
/* Since we aren't in D3 any more, it's safe to set this flag
|
|
* even if the controller was dead.
|
|
*/
|
|
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
|
mb();
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
|
|
/* FIXME: Disable non-PME# remote wakeup? */
|
|
|
|
/* The firmware or a boot kernel may have changed the controller
|
|
* settings during a system wakeup. Check it and reconfigure
|
|
* to avoid problems.
|
|
*/
|
|
check_and_reset_hc(uhci);
|
|
|
|
/* If the controller was dead before, it's back alive now */
|
|
configure_hc(uhci);
|
|
|
|
if (uhci->rh_state == UHCI_RH_RESET) {
|
|
|
|
/* The controller had to be reset */
|
|
usb_root_hub_lost_power(hcd->self.root_hub);
|
|
suspend_rh(uhci, UHCI_RH_SUSPENDED);
|
|
}
|
|
|
|
spin_unlock_irq(&uhci->lock);
|
|
|
|
if (!uhci->working_RD) {
|
|
/* Suspended root hub needs to be polled */
|
|
hcd->poll_rh = 1;
|
|
usb_hcd_poll_rh_status(hcd);
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/* Wait until a particular device/endpoint's QH is idle, and free it */
|
|
static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
|
|
struct usb_host_endpoint *hep)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
struct uhci_qh *qh;
|
|
|
|
spin_lock_irq(&uhci->lock);
|
|
qh = (struct uhci_qh *) hep->hcpriv;
|
|
if (qh == NULL)
|
|
goto done;
|
|
|
|
while (qh->state != QH_STATE_IDLE) {
|
|
++uhci->num_waiting;
|
|
spin_unlock_irq(&uhci->lock);
|
|
wait_event_interruptible(uhci->waitqh,
|
|
qh->state == QH_STATE_IDLE);
|
|
spin_lock_irq(&uhci->lock);
|
|
--uhci->num_waiting;
|
|
}
|
|
|
|
uhci_free_qh(uhci, qh);
|
|
done:
|
|
spin_unlock_irq(&uhci->lock);
|
|
}
|
|
|
|
static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
|
|
{
|
|
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
|
|
unsigned frame_number;
|
|
unsigned delta;
|
|
|
|
/* Minimize latency by avoiding the spinlock */
|
|
frame_number = uhci->frame_number;
|
|
barrier();
|
|
delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) &
|
|
(UHCI_NUMFRAMES - 1);
|
|
return frame_number + delta;
|
|
}
|
|
|
|
static const char hcd_name[] = "uhci_hcd";
|
|
|
|
static const struct hc_driver uhci_driver = {
|
|
.description = hcd_name,
|
|
.product_desc = "UHCI Host Controller",
|
|
.hcd_priv_size = sizeof(struct uhci_hcd),
|
|
|
|
/* Generic hardware linkage */
|
|
.irq = uhci_irq,
|
|
.flags = HCD_USB11,
|
|
|
|
/* Basic lifecycle operations */
|
|
.reset = uhci_init,
|
|
.start = uhci_start,
|
|
#ifdef CONFIG_PM
|
|
.suspend = uhci_suspend,
|
|
.resume = uhci_resume,
|
|
.bus_suspend = uhci_rh_suspend,
|
|
.bus_resume = uhci_rh_resume,
|
|
#endif
|
|
.stop = uhci_stop,
|
|
|
|
.urb_enqueue = uhci_urb_enqueue,
|
|
.urb_dequeue = uhci_urb_dequeue,
|
|
|
|
.endpoint_disable = uhci_hcd_endpoint_disable,
|
|
.get_frame_number = uhci_hcd_get_frame_number,
|
|
|
|
.hub_status_data = uhci_hub_status_data,
|
|
.hub_control = uhci_hub_control,
|
|
};
|
|
|
|
static const struct pci_device_id uhci_pci_ids[] = { {
|
|
/* handle any USB UHCI controller */
|
|
PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0),
|
|
.driver_data = (unsigned long) &uhci_driver,
|
|
}, { /* end: all zeroes */ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
|
|
|
|
static struct pci_driver uhci_pci_driver = {
|
|
.name = (char *)hcd_name,
|
|
.id_table = uhci_pci_ids,
|
|
|
|
.probe = usb_hcd_pci_probe,
|
|
.remove = usb_hcd_pci_remove,
|
|
.shutdown = uhci_shutdown,
|
|
|
|
#ifdef CONFIG_PM
|
|
.suspend = usb_hcd_pci_suspend,
|
|
.resume = usb_hcd_pci_resume,
|
|
#endif /* PM */
|
|
};
|
|
|
|
static int __init uhci_hcd_init(void)
|
|
{
|
|
int retval = -ENOMEM;
|
|
|
|
printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n");
|
|
|
|
if (usb_disabled())
|
|
return -ENODEV;
|
|
|
|
if (DEBUG_CONFIGURED) {
|
|
errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
|
|
if (!errbuf)
|
|
goto errbuf_failed;
|
|
uhci_debugfs_root = debugfs_create_dir("uhci", NULL);
|
|
if (!uhci_debugfs_root)
|
|
goto debug_failed;
|
|
}
|
|
|
|
uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
|
|
sizeof(struct urb_priv), 0, 0, NULL, NULL);
|
|
if (!uhci_up_cachep)
|
|
goto up_failed;
|
|
|
|
retval = pci_register_driver(&uhci_pci_driver);
|
|
if (retval)
|
|
goto init_failed;
|
|
|
|
return 0;
|
|
|
|
init_failed:
|
|
if (kmem_cache_destroy(uhci_up_cachep))
|
|
warn("not all urb_privs were freed!");
|
|
|
|
up_failed:
|
|
debugfs_remove(uhci_debugfs_root);
|
|
|
|
debug_failed:
|
|
kfree(errbuf);
|
|
|
|
errbuf_failed:
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void __exit uhci_hcd_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&uhci_pci_driver);
|
|
|
|
if (kmem_cache_destroy(uhci_up_cachep))
|
|
warn("not all urb_privs were freed!");
|
|
|
|
debugfs_remove(uhci_debugfs_root);
|
|
kfree(errbuf);
|
|
}
|
|
|
|
module_init(uhci_hcd_init);
|
|
module_exit(uhci_hcd_cleanup);
|
|
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL");
|