![Tony Lindgren](/assets/img/avatar_default.png)
Nowadays omap2 is booting in device tree only mode so there is no need to keep the legacy interface around for omap2_init_irq(). Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1421187806-6804-3-git-send-email-tony@atomide.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
407 lines
9.2 KiB
C
407 lines
9.2 KiB
C
/*
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* linux/arch/arm/mach-omap2/irq.c
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*
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* Interrupt handler for OMAP2 boards.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/exception.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "irqchip.h"
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/* Define these here for now until we drop all board-files */
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#define OMAP24XX_IC_BASE 0x480fe000
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#define OMAP34XX_IC_BASE 0x48200000
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/* selected INTC register offsets */
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#define INTC_REVISION 0x0000
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#define INTC_SYSCONFIG 0x0010
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#define INTC_SYSSTATUS 0x0014
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#define INTC_SIR 0x0040
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#define INTC_CONTROL 0x0048
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#define INTC_PROTECTION 0x004C
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#define INTC_IDLE 0x0050
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#define INTC_THRESHOLD 0x0068
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#define INTC_MIR0 0x0084
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#define INTC_MIR_CLEAR0 0x0088
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#define INTC_MIR_SET0 0x008c
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#define INTC_PENDING_IRQ0 0x0098
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#define INTC_PENDING_IRQ1 0x00b8
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#define INTC_PENDING_IRQ2 0x00d8
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#define INTC_PENDING_IRQ3 0x00f8
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#define INTC_ILR0 0x0100
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#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
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#define INTCPS_NR_ILR_REGS 128
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#define INTCPS_NR_MIR_REGS 4
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#define INTC_IDLE_FUNCIDLE (1 << 0)
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#define INTC_IDLE_TURBO (1 << 1)
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#define INTC_PROTECTION_ENABLE (1 << 0)
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struct omap_intc_regs {
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u32 sysconfig;
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u32 protection;
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u32 idle;
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u32 threshold;
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u32 ilr[INTCPS_NR_ILR_REGS];
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u32 mir[INTCPS_NR_MIR_REGS];
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};
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static struct omap_intc_regs intc_context;
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static struct irq_domain *domain;
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static void __iomem *omap_irq_base;
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static int omap_nr_pending = 3;
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static int omap_nr_irqs = 96;
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static void intc_writel(u32 reg, u32 val)
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{
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writel_relaxed(val, omap_irq_base + reg);
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}
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static u32 intc_readl(u32 reg)
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{
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return readl_relaxed(omap_irq_base + reg);
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}
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void omap_intc_save_context(void)
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{
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int i;
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intc_context.sysconfig =
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intc_readl(INTC_SYSCONFIG);
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intc_context.protection =
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intc_readl(INTC_PROTECTION);
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intc_context.idle =
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intc_readl(INTC_IDLE);
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intc_context.threshold =
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intc_readl(INTC_THRESHOLD);
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for (i = 0; i < omap_nr_irqs; i++)
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intc_context.ilr[i] =
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intc_readl((INTC_ILR0 + 0x4 * i));
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_context.mir[i] =
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intc_readl(INTC_MIR0 + (0x20 * i));
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}
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void omap_intc_restore_context(void)
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{
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int i;
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intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
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intc_writel(INTC_PROTECTION, intc_context.protection);
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intc_writel(INTC_IDLE, intc_context.idle);
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intc_writel(INTC_THRESHOLD, intc_context.threshold);
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for (i = 0; i < omap_nr_irqs; i++)
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intc_writel(INTC_ILR0 + 0x4 * i,
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intc_context.ilr[i]);
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_writel(INTC_MIR0 + 0x20 * i,
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intc_context.mir[i]);
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/* MIRs are saved and restore with other PRCM registers */
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}
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void omap3_intc_prepare_idle(void)
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{
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/*
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* Disable autoidle as it can stall interrupt controller,
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* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
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*/
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intc_writel(INTC_SYSCONFIG, 0);
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intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
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}
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void omap3_intc_resume_idle(void)
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{
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/* Re-enable autoidle */
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intc_writel(INTC_SYSCONFIG, 1);
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intc_writel(INTC_IDLE, 0);
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}
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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static void omap_ack_irq(struct irq_data *d)
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{
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intc_writel(INTC_CONTROL, 0x1);
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}
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static void omap_mask_ack_irq(struct irq_data *d)
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{
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irq_gc_mask_disable_reg(d);
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omap_ack_irq(d);
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}
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static void __init omap_irq_soft_reset(void)
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{
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unsigned long tmp;
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tmp = intc_readl(INTC_REVISION) & 0xff;
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pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
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omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
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tmp = intc_readl(INTC_SYSCONFIG);
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tmp |= 1 << 1; /* soft reset */
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intc_writel(INTC_SYSCONFIG, tmp);
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while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
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/* Wait for reset to complete */;
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/* Enable autoidle */
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intc_writel(INTC_SYSCONFIG, 1 << 0);
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}
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int omap_irq_pending(void)
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{
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int i;
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for (i = 0; i < omap_nr_pending; i++)
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if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
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return 1;
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return 0;
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}
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void omap3_intc_suspend(void)
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{
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/* A pending interrupt would prevent OMAP from entering suspend */
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omap_ack_irq(NULL);
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}
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static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
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{
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int ret;
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int i;
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ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
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handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
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IRQ_LEVEL, 0);
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if (ret) {
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pr_warn("Failed to allocate irq chips\n");
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return ret;
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}
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for (i = 0; i < omap_nr_pending; i++) {
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_get_domain_generic_chip(d, 32 * i);
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gc->reg_base = base;
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ct = gc->chip_types;
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ct->type = IRQ_TYPE_LEVEL_MASK;
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ct->handler = handle_level_irq;
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ct->chip.irq_ack = omap_mask_ack_irq;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
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ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
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ct->regs.disable = INTC_MIR_SET0 + 32 * i;
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}
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return 0;
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}
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static void __init omap_alloc_gc_legacy(void __iomem *base,
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unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_ack = omap_mask_ack_irq;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
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ct->regs.enable = INTC_MIR_CLEAR0;
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ct->regs.disable = INTC_MIR_SET0;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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static int __init omap_init_irq_of(struct device_node *node)
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{
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int ret;
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omap_irq_base = of_iomap(node, 0);
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if (WARN_ON(!omap_irq_base))
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return -ENOMEM;
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domain = irq_domain_add_linear(node, omap_nr_irqs,
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&irq_generic_chip_ops, NULL);
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omap_irq_soft_reset();
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ret = omap_alloc_gc_of(domain, omap_irq_base);
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if (ret < 0)
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irq_domain_remove(domain);
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return ret;
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}
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static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
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{
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int j, irq_base;
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omap_irq_base = ioremap(base, SZ_4K);
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if (WARN_ON(!omap_irq_base))
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return -ENOMEM;
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irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
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if (irq_base < 0) {
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pr_warn("Couldn't allocate IRQ numbers\n");
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irq_base = 0;
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}
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domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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omap_irq_soft_reset();
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for (j = 0; j < omap_nr_irqs; j += 32)
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omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
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return 0;
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}
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static void __init omap_irq_enable_protection(void)
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{
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u32 reg;
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reg = intc_readl(INTC_PROTECTION);
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reg |= INTC_PROTECTION_ENABLE;
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intc_writel(INTC_PROTECTION, reg);
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}
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static int __init omap_init_irq(u32 base, struct device_node *node)
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{
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int ret;
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/*
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* FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
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* depends is still not ready for linear IRQ domains; because of that
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* we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
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* linear IRQ Domain until that driver is finally fixed.
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*/
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if (of_device_is_compatible(node, "ti,omap2-intc") ||
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of_device_is_compatible(node, "ti,omap3-intc")) {
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struct resource res;
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if (of_address_to_resource(node, 0, &res))
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return -ENOMEM;
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base = res.start;
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ret = omap_init_irq_legacy(base, node);
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} else if (node) {
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ret = omap_init_irq_of(node);
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} else {
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ret = omap_init_irq_legacy(base, NULL);
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}
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if (ret == 0)
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omap_irq_enable_protection();
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return ret;
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}
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static asmlinkage void __exception_irq_entry
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omap_intc_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr = 0;
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int handled_irq = 0;
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int i;
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do {
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for (i = 0; i < omap_nr_pending; i++) {
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irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
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if (irqnr)
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goto out;
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}
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out:
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if (!irqnr)
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break;
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irqnr = intc_readl(INTC_SIR);
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irqnr &= ACTIVEIRQ_MASK;
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if (irqnr) {
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handle_domain_irq(domain, irqnr, regs);
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handled_irq = 1;
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}
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} while (irqnr);
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/*
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* If an irq is masked or deasserted while active, we will
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* keep ending up here with no irq handled. So remove it from
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* the INTC with an ack.
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*/
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if (!handled_irq)
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omap_ack_irq(NULL);
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}
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void __init omap3_init_irq(void)
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{
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omap_nr_irqs = 96;
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omap_nr_pending = 3;
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omap_init_irq(OMAP34XX_IC_BASE, NULL);
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set_handle_irq(omap_intc_handle_irq);
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}
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static int __init intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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int ret;
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omap_nr_pending = 3;
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omap_nr_irqs = 96;
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if (WARN_ON(!node))
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return -ENODEV;
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if (of_device_is_compatible(node, "ti,dm814-intc") ||
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of_device_is_compatible(node, "ti,dm816-intc") ||
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of_device_is_compatible(node, "ti,am33xx-intc")) {
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omap_nr_irqs = 128;
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omap_nr_pending = 4;
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}
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ret = omap_init_irq(-1, of_node_get(node));
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if (ret < 0)
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return ret;
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set_handle_irq(omap_intc_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
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IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
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IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init);
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IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init);
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IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);
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