559 lines
14 KiB
C
559 lines
14 KiB
C
/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* General FPU state handling cleanups
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* Gareth Hughes <gareth@valinux.com>, May 2000
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* x86-64 work by Andi Kleen 2002
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*/
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#ifndef _ASM_X86_FPU_INTERNAL_H
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#define _ASM_X86_FPU_INTERNAL_H
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#include <linux/regset.h>
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#include <linux/compat.h>
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#include <linux/slab.h>
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#include <asm/user.h>
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#include <asm/fpu/api.h>
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#include <asm/fpu/xsave.h>
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#ifdef CONFIG_X86_64
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# include <asm/sigcontext32.h>
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# include <asm/user32.h>
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struct ksignal;
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int ia32_setup_rt_frame(int sig, struct ksignal *ksig,
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compat_sigset_t *set, struct pt_regs *regs);
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int ia32_setup_frame(int sig, struct ksignal *ksig,
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compat_sigset_t *set, struct pt_regs *regs);
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#else
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# define user_i387_ia32_struct user_i387_struct
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# define user32_fxsr_struct user_fxsr_struct
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# define ia32_setup_frame __setup_frame
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# define ia32_setup_rt_frame __setup_rt_frame
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#endif
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#define MXCSR_DEFAULT 0x1f80
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extern unsigned int mxcsr_feature_mask;
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extern void fpu__cpu_init(void);
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extern void eager_fpu_init(void);
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DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
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extern void convert_from_fxsr(struct user_i387_ia32_struct *env,
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struct task_struct *tsk);
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extern void convert_to_fxsr(struct task_struct *tsk,
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const struct user_i387_ia32_struct *env);
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extern user_regset_active_fn regset_fpregs_active, regset_xregset_fpregs_active;
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extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
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xstateregs_get;
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extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
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xstateregs_set;
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/*
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* xstateregs_active == regset_fpregs_active. Please refer to the comment
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* at the definition of regset_fpregs_active.
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*/
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#define xstateregs_active regset_fpregs_active
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#ifdef CONFIG_MATH_EMULATION
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extern void finit_soft_fpu(struct i387_soft_struct *soft);
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#else
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static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
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#endif
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/*
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* Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx,
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* on this CPU.
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*
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* This will disable any lazy FPU state restore of the current FPU state,
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* but if the current thread owns the FPU, it will still be saved by.
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*/
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static inline void __cpu_disable_lazy_restore(unsigned int cpu)
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{
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per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
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}
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static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu)
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{
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return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
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}
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static inline int is_ia32_compat_frame(void)
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{
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return config_enabled(CONFIG_IA32_EMULATION) &&
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test_thread_flag(TIF_IA32);
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}
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static inline int is_ia32_frame(void)
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{
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return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame();
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}
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static inline int is_x32_frame(void)
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{
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return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32);
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}
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#define X87_FSW_ES (1 << 7) /* Exception Summary */
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static __always_inline __pure bool use_eager_fpu(void)
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{
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return static_cpu_has_safe(X86_FEATURE_EAGER_FPU);
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}
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static __always_inline __pure bool use_xsaveopt(void)
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{
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return static_cpu_has_safe(X86_FEATURE_XSAVEOPT);
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}
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static __always_inline __pure bool use_xsave(void)
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{
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return static_cpu_has_safe(X86_FEATURE_XSAVE);
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}
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static __always_inline __pure bool use_fxsr(void)
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{
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return static_cpu_has_safe(X86_FEATURE_FXSR);
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}
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static inline void fx_finit(struct i387_fxsave_struct *fx)
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{
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fx->cwd = 0x37f;
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fx->mxcsr = MXCSR_DEFAULT;
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}
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extern void __sanitize_i387_state(struct task_struct *);
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static inline void sanitize_i387_state(struct task_struct *tsk)
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{
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if (!use_xsaveopt())
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return;
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__sanitize_i387_state(tsk);
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}
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#define user_insn(insn, output, input...) \
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({ \
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int err; \
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asm volatile(ASM_STAC "\n" \
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"1:" #insn "\n\t" \
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"2: " ASM_CLAC "\n" \
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".section .fixup,\"ax\"\n" \
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"3: movl $-1,%[err]\n" \
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" jmp 2b\n" \
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".previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: [err] "=r" (err), output \
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: "0"(0), input); \
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err; \
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})
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#define check_insn(insn, output, input...) \
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({ \
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int err; \
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asm volatile("1:" #insn "\n\t" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: movl $-1,%[err]\n" \
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" jmp 2b\n" \
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".previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: [err] "=r" (err), output \
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: "0"(0), input); \
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err; \
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})
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static inline int fsave_user(struct i387_fsave_struct __user *fx)
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{
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return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
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}
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static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
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{
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if (config_enabled(CONFIG_X86_32))
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return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
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else if (config_enabled(CONFIG_AS_FXSAVEQ))
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return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
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/* See comment in fpu_fxsave() below. */
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return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
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}
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static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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{
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if (config_enabled(CONFIG_X86_32))
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return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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else if (config_enabled(CONFIG_AS_FXSAVEQ))
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return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
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/* See comment in fpu_fxsave() below. */
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return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
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"m" (*fx));
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}
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static inline int fxrstor_user(struct i387_fxsave_struct __user *fx)
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{
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if (config_enabled(CONFIG_X86_32))
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return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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else if (config_enabled(CONFIG_AS_FXSAVEQ))
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return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
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/* See comment in fpu_fxsave() below. */
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return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
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"m" (*fx));
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}
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static inline int frstor_checking(struct i387_fsave_struct *fx)
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{
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return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline int frstor_user(struct i387_fsave_struct __user *fx)
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{
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return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline void fpu_fxsave(struct fpu *fpu)
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{
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if (config_enabled(CONFIG_X86_32))
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asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave));
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else if (config_enabled(CONFIG_AS_FXSAVEQ))
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asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state->fxsave));
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else {
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/* Using "rex64; fxsave %0" is broken because, if the memory
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* operand uses any extended registers for addressing, a second
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* REX prefix will be generated (to the assembler, rex64
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* followed by semicolon is a separate instruction), and hence
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* the 64-bitness is lost.
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*
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* Using "fxsaveq %0" would be the ideal choice, but is only
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* supported starting with gas 2.16.
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*
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* Using, as a workaround, the properly prefixed form below
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* isn't accepted by any binutils version so far released,
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* complaining that the same type of prefix is used twice if
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* an extended register is needed for addressing (fix submitted
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* to mainline 2005-11-21).
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*
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* asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave));
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*
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* This, however, we can work around by forcing the compiler to
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* select an addressing mode that doesn't require extended
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* registers.
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*/
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asm volatile( "rex64/fxsave (%[fx])"
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: "=m" (fpu->state->fxsave)
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: [fx] "R" (&fpu->state->fxsave));
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}
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}
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/*
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* These must be called with preempt disabled. Returns
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* 'true' if the FPU state is still intact.
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*/
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static inline int fpu_save_init(struct fpu *fpu)
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{
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if (use_xsave()) {
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xsave_state(&fpu->state->xsave);
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/*
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* xsave header may indicate the init state of the FP.
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*/
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if (!(fpu->state->xsave.header.xfeatures & XSTATE_FP))
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return 1;
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} else if (use_fxsr()) {
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fpu_fxsave(fpu);
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} else {
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asm volatile("fnsave %[fx]; fwait"
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: [fx] "=m" (fpu->state->fsave));
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return 0;
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}
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/*
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* If exceptions are pending, we need to clear them so
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* that we don't randomly get exceptions later.
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*
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* FIXME! Is this perhaps only true for the old-style
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* irq13 case? Maybe we could leave the x87 state
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* intact otherwise?
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*/
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if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
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asm volatile("fnclex");
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return 0;
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}
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return 1;
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}
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static inline int fpu_restore_checking(struct fpu *fpu)
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{
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if (use_xsave())
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return fpu_xrstor_checking(&fpu->state->xsave);
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else if (use_fxsr())
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return fxrstor_checking(&fpu->state->fxsave);
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else
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return frstor_checking(&fpu->state->fsave);
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}
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static inline int restore_fpu_checking(struct fpu *fpu)
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{
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/*
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* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
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* pending. Clear the x87 state here by setting it to fixed values.
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* "m" is a random variable that should be in L1.
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*/
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if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) {
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asm volatile(
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"fnclex\n\t"
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"emms\n\t"
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"fildl %P[addr]" /* set F?P to defined value */
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: : [addr] "m" (fpu->fpregs_active));
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}
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return fpu_restore_checking(fpu);
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}
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/* Must be paired with an 'stts' after! */
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static inline void __thread_clear_has_fpu(struct fpu *fpu)
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{
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fpu->fpregs_active = 0;
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this_cpu_write(fpu_fpregs_owner_ctx, NULL);
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}
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/* Must be paired with a 'clts' before! */
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static inline void __thread_set_has_fpu(struct fpu *fpu)
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{
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fpu->fpregs_active = 1;
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this_cpu_write(fpu_fpregs_owner_ctx, fpu);
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}
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/*
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* Encapsulate the CR0.TS handling together with the
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* software flag.
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*
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* These generally need preemption protection to work,
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* do try to avoid using these on their own.
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*/
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static inline void __thread_fpu_end(struct fpu *fpu)
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{
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__thread_clear_has_fpu(fpu);
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if (!use_eager_fpu())
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stts();
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}
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static inline void __thread_fpu_begin(struct fpu *fpu)
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{
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if (!use_eager_fpu())
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clts();
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__thread_set_has_fpu(fpu);
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}
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static inline void drop_fpu(struct fpu *fpu)
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{
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/*
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* Forget coprocessor state..
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*/
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preempt_disable();
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fpu->counter = 0;
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if (fpu->fpregs_active) {
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/* Ignore delayed exceptions from user space */
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asm volatile("1: fwait\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b));
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__thread_fpu_end(fpu);
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}
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fpu->fpstate_active = 0;
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preempt_enable();
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}
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static inline void restore_init_xstate(void)
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{
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if (use_xsave())
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xrstor_state(init_xstate_buf, -1);
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else
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fxrstor_checking(&init_xstate_buf->i387);
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}
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/*
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* Reset the FPU state in the eager case and drop it in the lazy case (later use
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* will reinit it).
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*/
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static inline void fpu_reset_state(struct fpu *fpu)
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{
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if (!use_eager_fpu())
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drop_fpu(fpu);
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else
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restore_init_xstate();
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}
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/*
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* FPU state switching for scheduling.
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*
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* This is a two-stage process:
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*
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* - switch_fpu_prepare() saves the old state and
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* sets the new state of the CR0.TS bit. This is
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* done within the context of the old process.
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*
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* - switch_fpu_finish() restores the new state as
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* necessary.
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*/
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typedef struct { int preload; } fpu_switch_t;
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static inline fpu_switch_t
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switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu)
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{
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fpu_switch_t fpu;
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/*
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* If the task has used the math, pre-load the FPU on xsave processors
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* or if the past 5 consecutive context-switches used math.
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*/
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fpu.preload = new_fpu->fpstate_active &&
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(use_eager_fpu() || new_fpu->counter > 5);
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if (old_fpu->fpregs_active) {
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if (!fpu_save_init(old_fpu))
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old_fpu->last_cpu = -1;
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else
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old_fpu->last_cpu = cpu;
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/* But leave fpu_fpregs_owner_ctx! */
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old_fpu->fpregs_active = 0;
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/* Don't change CR0.TS if we just switch! */
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if (fpu.preload) {
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new_fpu->counter++;
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__thread_set_has_fpu(new_fpu);
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prefetch(new_fpu->state);
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} else if (!use_eager_fpu())
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stts();
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} else {
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old_fpu->counter = 0;
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old_fpu->last_cpu = -1;
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if (fpu.preload) {
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new_fpu->counter++;
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if (fpu_want_lazy_restore(new_fpu, cpu))
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fpu.preload = 0;
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else
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prefetch(new_fpu->state);
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__thread_fpu_begin(new_fpu);
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}
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}
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return fpu;
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}
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/*
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* By the time this gets called, we've already cleared CR0.TS and
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* given the process the FPU if we are going to preload the FPU
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* state - all we need to do is to conditionally restore the register
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* state itself.
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*/
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static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch)
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{
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if (fpu_switch.preload) {
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if (unlikely(restore_fpu_checking(new_fpu)))
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fpu_reset_state(new_fpu);
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}
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}
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/*
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* Signal frame handlers...
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*/
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extern int save_xstate_sig(void __user *buf, void __user *fx, int size);
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extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size);
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static inline int xstate_sigframe_size(void)
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{
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return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size;
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}
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static inline int restore_xstate_sig(void __user *buf, int ia32_frame)
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{
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void __user *buf_fx = buf;
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int size = xstate_sigframe_size();
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if (ia32_frame && use_fxsr()) {
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buf_fx = buf + sizeof(struct i387_fsave_struct);
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size += sizeof(struct i387_fsave_struct);
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}
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return __restore_xstate_sig(buf, buf_fx, size);
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}
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/*
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* Needs to be preemption-safe.
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*
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* NOTE! user_fpu_begin() must be used only immediately before restoring
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* the save state. It does not do any saving/restoring on its own. In
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* lazy FPU mode, it is just an optimization to avoid a #NM exception,
|
|
* the task can lose the FPU right after preempt_enable().
|
|
*/
|
|
static inline void user_fpu_begin(void)
|
|
{
|
|
struct fpu *fpu = ¤t->thread.fpu;
|
|
|
|
preempt_disable();
|
|
if (!user_has_fpu())
|
|
__thread_fpu_begin(fpu);
|
|
preempt_enable();
|
|
}
|
|
|
|
/*
|
|
* i387 state interaction
|
|
*/
|
|
static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
|
|
{
|
|
if (cpu_has_fxsr) {
|
|
return tsk->thread.fpu.state->fxsave.cwd;
|
|
} else {
|
|
return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
|
|
}
|
|
}
|
|
|
|
static inline unsigned short get_fpu_swd(struct task_struct *tsk)
|
|
{
|
|
if (cpu_has_fxsr) {
|
|
return tsk->thread.fpu.state->fxsave.swd;
|
|
} else {
|
|
return (unsigned short)tsk->thread.fpu.state->fsave.swd;
|
|
}
|
|
}
|
|
|
|
static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
|
|
{
|
|
if (cpu_has_xmm) {
|
|
return tsk->thread.fpu.state->fxsave.mxcsr;
|
|
} else {
|
|
return MXCSR_DEFAULT;
|
|
}
|
|
}
|
|
|
|
extern void fpstate_cache_init(void);
|
|
|
|
extern int fpstate_alloc(struct fpu *fpu);
|
|
extern void fpstate_free(struct fpu *fpu);
|
|
extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu);
|
|
|
|
static inline unsigned long
|
|
alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx,
|
|
unsigned long *size)
|
|
{
|
|
unsigned long frame_size = xstate_sigframe_size();
|
|
|
|
*buf_fx = sp = round_down(sp - frame_size, 64);
|
|
if (ia32_frame && use_fxsr()) {
|
|
frame_size += sizeof(struct i387_fsave_struct);
|
|
sp -= sizeof(struct i387_fsave_struct);
|
|
}
|
|
|
|
*size = frame_size;
|
|
return sp;
|
|
}
|
|
|
|
#endif /* _ASM_X86_FPU_INTERNAL_H */
|