![Omar Ramirez Luna](/assets/img/avatar_default.png)
In order to detect it at runtime, we need the code handling wdt clock available at runtime to decide whether to enable or disable based on the baseimage symbols. Default timeout has been set to 5 seconds. Downside is that we will lose the option to set a custom timeout for overflow, but than can be added (if needed) as part of debugfs. Signed-off-by: Omar Ramirez <omar.ramirez@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
178 lines
5.4 KiB
C
178 lines
5.4 KiB
C
/*
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* _chnl_sm.h
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* Private header file defining channel manager and channel objects for
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* a shared memory channel driver.
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*
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* Shared between the modules implementing the shared memory channel class
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* library.
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#ifndef _CHNL_SM_
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#define _CHNL_SM_
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#include <dspbridge/dspapi.h>
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#include <dspbridge/dspdefs.h>
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#include <linux/list.h>
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#include <dspbridge/ntfy.h>
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/*
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* These target side symbols define the beginning and ending addresses
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* of shared memory buffer. They are defined in the *cfg.cmd file by
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* cdb code.
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*/
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#define CHNL_SHARED_BUFFER_BASE_SYM "_SHM_BEG"
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#define CHNL_SHARED_BUFFER_LIMIT_SYM "_SHM_END"
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#define BRIDGEINIT_BIOSGPTIMER "_BRIDGEINIT_BIOSGPTIMER"
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#define BRIDGEINIT_LOADMON_GPTIMER "_BRIDGEINIT_LOADMON_GPTIMER"
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#ifndef _CHNL_WORDSIZE
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#define _CHNL_WORDSIZE 4 /* default _CHNL_WORDSIZE is 2 bytes/word */
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#endif
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#define MAXOPPS 16
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/* Shared memory config options */
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#define SHM_CURROPP 0 /* Set current OPP in shm */
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#define SHM_OPPINFO 1 /* Set dsp voltage and freq table values */
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#define SHM_GETOPP 2 /* Get opp requested by DSP */
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struct opp_table_entry {
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u32 voltage;
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u32 frequency;
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u32 min_freq;
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u32 max_freq;
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};
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struct opp_struct {
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u32 curr_opp_pt;
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u32 num_opp_pts;
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struct opp_table_entry opp_point[MAXOPPS];
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};
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/* Request to MPU */
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struct opp_rqst_struct {
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u32 rqst_dsp_freq;
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u32 rqst_opp_pt;
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};
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/* Info to MPU */
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struct load_mon_struct {
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u32 curr_dsp_load;
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u32 curr_dsp_freq;
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u32 pred_dsp_load;
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u32 pred_dsp_freq;
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};
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/* Structure in shared between DSP and PC for communication. */
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struct shm {
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u32 dsp_free_mask; /* Written by DSP, read by PC. */
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u32 host_free_mask; /* Written by PC, read by DSP */
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u32 input_full; /* Input channel has unread data. */
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u32 input_id; /* Channel for which input is available. */
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u32 input_size; /* Size of data block (in DSP words). */
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u32 output_full; /* Output channel has unread data. */
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u32 output_id; /* Channel for which output is available. */
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u32 output_size; /* Size of data block (in DSP words). */
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u32 arg; /* Arg for Issue/Reclaim (23 bits for 55x). */
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u32 resvd; /* Keep structure size even for 32-bit DSPs */
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/* Operating Point structure */
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struct opp_struct opp_table_struct;
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/* Operating Point Request structure */
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struct opp_rqst_struct opp_request;
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/* load monitor information structure */
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struct load_mon_struct load_mon_info;
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/* Flag for WDT enable/disable F/I clocks */
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u32 wdt_setclocks;
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u32 wdt_overflow; /* WDT overflow time */
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char dummy[176]; /* padding to 256 byte boundary */
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u32 shm_dbg_var[64]; /* shared memory debug variables */
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};
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/* Channel Manager: only one created per board: */
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struct chnl_mgr {
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/* Function interface to Bridge driver */
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struct bridge_drv_interface *intf_fxns;
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struct io_mgr *iomgr; /* IO manager */
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/* Device this board represents */
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struct dev_object *dev_obj;
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/* These fields initialized in bridge_chnl_create(): */
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u32 output_mask; /* Host output channels w/ full buffers */
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u32 last_output; /* Last output channel fired from DPC */
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/* Critical section object handle */
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spinlock_t chnl_mgr_lock;
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u32 word_size; /* Size in bytes of DSP word */
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u8 max_channels; /* Total number of channels */
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u8 open_channels; /* Total number of open channels */
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struct chnl_object **channels; /* Array of channels */
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u8 type; /* Type of channel class library */
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/* If no shm syms, return for CHNL_Open */
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int chnl_open_status;
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};
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/*
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* Channel: up to CHNL_MAXCHANNELS per board or if DSP-DMA supported then
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* up to CHNL_MAXCHANNELS + CHNL_MAXDDMACHNLS per board.
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*/
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struct chnl_object {
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/* Pointer back to channel manager */
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struct chnl_mgr *chnl_mgr_obj;
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u32 chnl_id; /* Channel id */
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u8 state; /* Current channel state */
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s8 chnl_mode; /* Chnl mode and attributes */
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/* Chnl I/O completion event (user mode) */
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void *user_event;
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/* Abstract synchronization object */
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struct sync_object *sync_event;
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u32 process; /* Process which created this channel */
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u32 cb_arg; /* Argument to use with callback */
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struct list_head io_requests; /* List of IOR's to driver */
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s32 cio_cs; /* Number of IOC's in queue */
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s32 cio_reqs; /* Number of IORequests in queue */
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s32 chnl_packets; /* Initial number of free Irps */
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/* List of IOC's from driver */
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struct list_head io_completions;
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struct list_head free_packets_list; /* List of free Irps */
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struct ntfy_object *ntfy_obj;
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u32 bytes_moved; /* Total number of bytes transferred */
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/* For DSP-DMA */
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/* Type of chnl transport:CHNL_[PCPY][DDMA] */
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u32 chnl_type;
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};
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/* I/O Request/completion packet: */
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struct chnl_irp {
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struct list_head link; /* Link to next CHIRP in queue. */
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/* Buffer to be filled/emptied. (User) */
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u8 *host_user_buf;
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/* Buffer to be filled/emptied. (System) */
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u8 *host_sys_buf;
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u32 arg; /* Issue/Reclaim argument. */
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u32 dsp_tx_addr; /* Transfer address on DSP side. */
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u32 byte_size; /* Bytes transferred. */
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u32 buf_size; /* Actual buffer size when allocated. */
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u32 status; /* Status of IO completion. */
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};
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#endif /* _CHNL_SM_ */
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