daeb4c0c3b
Most PCI implementations use the standard PCI swizzle function, which handles the well defined behaviour of PCI-to-PCI bridges which can be found on cards (eg, four port ethernet cards.) Rather than having almost every platform specify the standard swizzle function, make this the default when no swizzle function is supplied. Therefore, a swizzle function only needs to be provided when there is something exceptional which needs to be handled. This gets rid of the swizzle initializer from 47 files, and leaves us with just two platforms specifying a swizzle function: ARM Integrator and Chalice CATS. Acked-by: Krzysztof Hałasa <khc@pm.waw.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/*
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* iq81340sc board support
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* Copyright (c) 2005-2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/pci.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/pci.h>
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#include <asm/mach/time.h>
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#include <mach/time.h>
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extern int init_atu;
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static int __init
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iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
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{
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WARN_ON(idsel < 1 || idsel > 2);
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switch (idsel) {
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case 1:
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switch (pin) {
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case 1: return ATUX_INTB;
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case 2: return ATUX_INTC;
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case 3: return ATUX_INTD;
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case 4: return ATUX_INTA;
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default: return -1;
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}
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case 2:
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switch (pin) {
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case 1: return ATUX_INTC;
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case 2: return ATUX_INTC;
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case 3: return ATUX_INTC;
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case 4: return ATUX_INTC;
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default: return -1;
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}
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default: return -1;
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}
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}
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static struct hw_pci iq81340sc_pci __initdata = {
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.nr_controllers = 0,
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.setup = iop13xx_pci_setup,
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.scan = iop13xx_scan_bus,
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.map_irq = iq81340sc_atux_map_irq,
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.preinit = iop13xx_pci_init
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};
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static int __init iq81340sc_pci_init(void)
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{
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iop13xx_atu_select(&iq81340sc_pci);
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pci_common_init(&iq81340sc_pci);
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iop13xx_map_pci_memory();
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return 0;
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}
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static void __init iq81340sc_init(void)
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{
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iop13xx_platform_init();
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iq81340sc_pci_init();
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iop13xx_add_tpmi_devices();
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}
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static void __init iq81340sc_timer_init(void)
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{
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unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
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printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
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iop_init_time(bus_freq);
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}
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static struct sys_timer iq81340sc_timer = {
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.init = iq81340sc_timer_init,
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};
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MACHINE_START(IQ81340SC, "Intel IQ81340SC")
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/* Maintainer: Dan Williams <dan.j.williams@intel.com> */
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.atag_offset = 0x100,
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.init_early = iop13xx_init_early,
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.map_io = iop13xx_map_io,
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.init_irq = iop13xx_init_irq,
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.timer = &iq81340sc_timer,
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.init_machine = iq81340sc_init,
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.restart = iop13xx_restart,
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MACHINE_END
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