76a323c19a
The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
88 lines
1.9 KiB
C
88 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017~2018 NXP
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define PCG_PCS_SHIFT 24
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#define PCG_PCS_MASK 0x7
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#define PCG_CGC_SHIFT 30
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#define PCG_FRAC_SHIFT 3
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#define PCG_FRAC_WIDTH 1
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#define PCG_FRAC_MASK BIT(3)
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#define PCG_PCD_SHIFT 0
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#define PCG_PCD_WIDTH 3
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#define PCG_PCD_MASK 0x7
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struct clk_hw *imx7ulp_clk_composite(const char *name,
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const char * const *parent_names,
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int num_parents, bool mux_present,
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bool rate_present, bool gate_present,
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void __iomem *reg)
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{
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struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
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struct clk_fractional_divider *fd = NULL;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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struct clk_hw *hw;
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if (mux_present) {
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux_hw = &mux->hw;
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mux->reg = reg;
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mux->shift = PCG_PCS_SHIFT;
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mux->mask = PCG_PCS_MASK;
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}
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if (rate_present) {
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd) {
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kfree(mux);
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return ERR_PTR(-ENOMEM);
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}
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fd_hw = &fd->hw;
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fd->reg = reg;
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fd->mshift = PCG_FRAC_SHIFT;
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fd->mwidth = PCG_FRAC_WIDTH;
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fd->mmask = PCG_FRAC_MASK;
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fd->nshift = PCG_PCD_SHIFT;
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fd->nwidth = PCG_PCD_WIDTH;
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fd->nmask = PCG_PCD_MASK;
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fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
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}
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if (gate_present) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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kfree(mux);
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kfree(fd);
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return ERR_PTR(-ENOMEM);
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}
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gate_hw = &gate->hw;
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gate->reg = reg;
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gate->bit_idx = PCG_CGC_SHIFT;
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}
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, &clk_mux_ops, fd_hw,
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&clk_fractional_divider_ops, gate_hw,
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&clk_gate_ops, CLK_SET_RATE_GATE |
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CLK_SET_PARENT_GATE);
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if (IS_ERR(hw)) {
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kfree(mux);
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kfree(fd);
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kfree(gate);
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}
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return hw;
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}
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