9c92ab6191
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/export.h>
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#include "clk-regmap-divider.h"
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static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
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{
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return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
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}
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static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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struct clk_regmap *clkr = ÷r->clkr;
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u32 val;
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regmap_read(clkr->regmap, divider->reg, &val);
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val >>= divider->shift;
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val &= BIT(divider->width) - 1;
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return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
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CLK_DIVIDER_ROUND_CLOSEST, val);
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}
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static long div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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return divider_round_rate(hw, rate, prate, NULL, divider->width,
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CLK_DIVIDER_ROUND_CLOSEST);
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}
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static int div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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struct clk_regmap *clkr = ÷r->clkr;
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u32 div;
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div = divider_get_val(rate, parent_rate, NULL, divider->width,
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CLK_DIVIDER_ROUND_CLOSEST);
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return regmap_update_bits(clkr->regmap, divider->reg,
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(BIT(divider->width) - 1) << divider->shift,
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div << divider->shift);
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}
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static unsigned long div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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struct clk_regmap *clkr = ÷r->clkr;
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u32 div;
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regmap_read(clkr->regmap, divider->reg, &div);
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div >>= divider->shift;
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div &= BIT(divider->width) - 1;
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return divider_recalc_rate(hw, parent_rate, div, NULL,
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CLK_DIVIDER_ROUND_CLOSEST, divider->width);
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}
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const struct clk_ops clk_regmap_div_ops = {
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.round_rate = div_round_rate,
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.set_rate = div_set_rate,
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.recalc_rate = div_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
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const struct clk_ops clk_regmap_div_ro_ops = {
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.round_rate = div_round_ro_rate,
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.recalc_rate = div_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);
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