b06a532bf1
Exynos5250/5420/5800 have only one clock controller, but some of their clock depends on respective power domains. Handling integration of clock controller and power domain can be done using runtime PM feature of CCF framework. This however needs a separate struct device for each power domain. This patch adds such separate driver for a group of such clocks, which can be instantiated more than once, each time for a different power domain. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
27 lines
589 B
C
27 lines
589 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __CLK_EXYNOS5_SUBCMU_H
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#define __CLK_EXYNOS5_SUBCMU_H
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struct exynos5_subcmu_reg_dump {
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u32 offset;
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u32 value;
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u32 mask;
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u32 save;
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};
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struct exynos5_subcmu_info {
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const struct samsung_div_clock *div_clks;
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unsigned int nr_div_clks;
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const struct samsung_gate_clock *gate_clks;
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unsigned int nr_gate_clks;
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struct exynos5_subcmu_reg_dump *suspend_regs;
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unsigned int nr_suspend_regs;
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const char *pd_name;
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};
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void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus,
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const struct exynos5_subcmu_info *cmu);
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#endif
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