9952f6918d
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
123 lines
2.9 KiB
C
123 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk/tegra.h>
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#include "clk.h"
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#include "clk-id.h"
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#define PMC_CLK_OUT_CNTRL 0x1a8
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#define PMC_DPD_PADS_ORIDE 0x1c
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#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
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#define PMC_CTRL 0
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#define PMC_CTRL_BLINK_ENB 7
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#define PMC_BLINK_TIMER 0x40
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struct pmc_clk_init_data {
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char *mux_name;
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char *gate_name;
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const char **parents;
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int num_parents;
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int mux_id;
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int gate_id;
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char *dev_name;
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u8 mux_shift;
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u8 gate_shift;
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};
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#define PMC_CLK(_num, _mux_shift, _gate_shift)\
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{\
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.mux_name = "clk_out_" #_num "_mux",\
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.gate_name = "clk_out_" #_num,\
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.parents = clk_out ##_num ##_parents,\
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.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
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.mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
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.gate_id = tegra_clk_clk_out_ ##_num,\
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.dev_name = "extern" #_num,\
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.mux_shift = _mux_shift,\
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.gate_shift = _gate_shift,\
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}
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static DEFINE_SPINLOCK(clk_out_lock);
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static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern1",
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};
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static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern2",
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};
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static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
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"clk_m_div4", "extern3",
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};
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static struct pmc_clk_init_data pmc_clks[] = {
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PMC_CLK(1, 6, 2),
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PMC_CLK(2, 14, 10),
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PMC_CLK(3, 22, 18),
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};
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void __init tegra_pmc_clk_init(void __iomem *pmc_base,
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struct tegra_clk *tegra_clks)
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{
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struct clk *clk;
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struct clk **dt_clk;
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int i;
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for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
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struct pmc_clk_init_data *data;
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data = pmc_clks + i;
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dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = clk_register_mux(NULL, data->mux_name, data->parents,
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data->num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
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pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
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3, 0, &clk_out_lock);
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*dt_clk = clk;
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dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
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if (!dt_clk)
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continue;
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clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
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CLK_SET_RATE_PARENT,
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pmc_base + PMC_CLK_OUT_CNTRL,
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data->gate_shift, 0, &clk_out_lock);
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*dt_clk = clk;
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clk_register_clkdev(clk, data->dev_name, data->gate_name);
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}
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/* blink */
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writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
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clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
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pmc_base + PMC_DPD_PADS_ORIDE,
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PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
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dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
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if (!dt_clk)
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return;
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clk = clk_register_gate(NULL, "blink", "blink_override", 0,
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pmc_base + PMC_CTRL,
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PMC_CTRL_BLINK_ENB, 0, NULL);
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clk_register_clkdev(clk, "blink", NULL);
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*dt_clk = clk;
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}
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