6a31061833
We lose even config space access when we power gate the ISP via the PUNIT. That makes lspci & co. produce gibberish. To fix that let's try to implement actual runtime pm hooks and inform the pci core that the device always goes to D3cold. That will cause the pci core to resume the device before attempting config space access. This introduces another annoyance though. We get the following error every time we try to resume the device: intel_atomisp2_pm 0000:00:03.0: Refused to change power state, currently in D3 The reason being that the pci core tries to put the device back into D0 via the standard PCI PM mechanism before calling the driver resume hook. To fix this properly we'd need to infiltrate the platform pm hooks (could turn ugly real fast), or use pm domains (which don't seem to exist on x86), or some extra early resume hook for the driver (which doesn't exist either). So maybe we just choose to live with the error? Cc: Hans de Goede <hdegoede@redhat.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Darren Hart <dvhart@infradead.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
149 lines
3.8 KiB
C
149 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Dummy driver for Intel's Image Signal Processor found on Bay and Cherry
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* Trail devices. The sole purpose of this driver is to allow the ISP to
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* be put in D3.
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*
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* Copyright (C) 2018 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on various non upstream patches for ISP support:
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* Copyright (C) 2010-2017 Intel Corporation. All rights reserved.
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* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
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*/
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <asm/iosf_mbi.h>
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/* PCI configuration regs */
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#define PCI_INTERRUPT_CTRL 0x9c
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#define PCI_CSI_CONTROL 0xe8
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#define PCI_CSI_CONTROL_PORTS_OFF_MASK 0x7
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/* IOSF BT_MBI_UNIT_PMC regs */
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#define ISPSSPM0 0x39
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#define ISPSSPM0_ISPSSC_OFFSET 0
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#define ISPSSPM0_ISPSSC_MASK 0x00000003
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#define ISPSSPM0_ISPSSS_OFFSET 24
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#define ISPSSPM0_ISPSSS_MASK 0x03000000
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#define ISPSSPM0_IUNIT_POWER_ON 0x0
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#define ISPSSPM0_IUNIT_POWER_OFF 0x3
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static int isp_set_power(struct pci_dev *dev, bool enable)
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{
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unsigned long timeout;
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u32 val = enable ? ISPSSPM0_IUNIT_POWER_ON :
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ISPSSPM0_IUNIT_POWER_OFF;
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/* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
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iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM0,
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val, ISPSSPM0_ISPSSC_MASK);
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/*
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* There should be no IUNIT access while power-down is
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* in progress HW sighting: 4567865
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* Wait up to 50 ms for the IUNIT to shut down.
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* And we do the same for power on.
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*/
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timeout = jiffies + msecs_to_jiffies(50);
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while (1) {
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u32 tmp;
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/* Wait until ISPSSPM0 bit[25:24] shows the right value */
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iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, ISPSSPM0, &tmp);
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tmp = (tmp & ISPSSPM0_ISPSSS_MASK) >> ISPSSPM0_ISPSSS_OFFSET;
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if (tmp == val)
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break;
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if (time_after(jiffies, timeout)) {
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dev_err(&dev->dev, "IUNIT power-%s timeout.\n",
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enable ? "on" : "off");
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return -EBUSY;
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}
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usleep_range(1000, 2000);
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}
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return 0;
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}
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static int isp_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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pm_runtime_allow(&dev->dev);
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pm_runtime_put_sync_suspend(&dev->dev);
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return 0;
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}
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static void isp_remove(struct pci_dev *dev)
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{
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pm_runtime_get_sync(&dev->dev);
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pm_runtime_forbid(&dev->dev);
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}
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static int isp_pci_suspend(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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u32 val;
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pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, 0);
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/*
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* MRFLD IUNIT DPHY is located in an always-power-on island
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* MRFLD HW design need all CSI ports are disabled before
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* powering down the IUNIT.
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*/
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pci_read_config_dword(pdev, PCI_CSI_CONTROL, &val);
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val |= PCI_CSI_CONTROL_PORTS_OFF_MASK;
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pci_write_config_dword(pdev, PCI_CSI_CONTROL, val);
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/*
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* We lose config space access when punit power gates
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* the ISP. Can't use pci_set_power_state() because
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* pmcsr won't actually change when we write to it.
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*/
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pci_save_state(pdev);
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pdev->current_state = PCI_D3cold;
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isp_set_power(pdev, false);
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return 0;
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}
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static int isp_pci_resume(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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isp_set_power(pdev, true);
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pdev->current_state = PCI_D0;
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pci_restore_state(pdev);
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return 0;
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}
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static UNIVERSAL_DEV_PM_OPS(isp_pm_ops, isp_pci_suspend,
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isp_pci_resume, NULL);
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static const struct pci_device_id isp_id_table[] = {
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{ PCI_VDEVICE(INTEL, 0x0f38), },
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{ PCI_VDEVICE(INTEL, 0x22b8), },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, isp_id_table);
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static struct pci_driver isp_pci_driver = {
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.name = "intel_atomisp2_pm",
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.id_table = isp_id_table,
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.probe = isp_probe,
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.remove = isp_remove,
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.driver.pm = &isp_pm_ops,
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};
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module_pci_driver(isp_pci_driver);
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MODULE_DESCRIPTION("Intel AtomISP2 dummy / power-management drv (for suspend)");
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MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
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MODULE_LICENSE("GPL v2");
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