![Paul Walmsley](/assets/img/avatar_default.png)
Now that almost all of the code has been removed from clock2xxx.c and clock34xx.c, many of the includes are now unnecessary and can be removed. While we're here, standardize the initial comment blocks. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Jouni Högander <jouni.hogander@nokia.com>
239 lines
6.5 KiB
C
239 lines
6.5 KiB
C
/*
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* OMAP3-specific clock framework functions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "clock34xx.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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/*
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* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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* to be at 120 MHz for proper operation.
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*/
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#define DPLL5_FREQ_FOR_USBHOST 120000000
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/* needed by omap3_core_dpll_m2_set_rate() */
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struct clk *sdrc_ick_p, *arm_fck_p;
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/**
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* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
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* @clk: struct clk * being enabled
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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*
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* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
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* from the CM_{I,F}CLKEN bit. Pass back the correct info via
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* @idlest_reg and @idlest_bit. No return value.
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*/
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static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
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void __iomem **idlest_reg,
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u8 *idlest_bit)
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{
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u32 r;
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r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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*idlest_reg = (__force void __iomem *)r;
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*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
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}
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const struct clkops clkops_omap3430es2_ssi_wait = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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.find_idlest = omap3430es2_clk_ssi_find_idlest,
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.find_companion = omap2_clk_dflt_find_companion,
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};
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/**
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* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
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* @clk: struct clk * being enabled
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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*
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* Some OMAP modules on OMAP3 ES2+ chips have both initiator and
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* target IDLEST bits. For our purposes, we are concerned with the
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* target IDLEST bits, which exist at a different bit position than
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* the *CLKEN bit position for these modules (DSS and USBHOST) (The
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* default find_idlest code assumes that they are at the same
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* position.) No return value.
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*/
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static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
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void __iomem **idlest_reg,
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u8 *idlest_bit)
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{
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u32 r;
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r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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*idlest_reg = (__force void __iomem *)r;
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/* USBHOST_IDLE has same shift */
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*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
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}
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const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
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.find_companion = omap2_clk_dflt_find_companion,
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};
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/**
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* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
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* @clk: struct clk * being enabled
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* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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*
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* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
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* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
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* @idlest_reg and @idlest_bit. No return value.
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*/
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static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
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void __iomem **idlest_reg,
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u8 *idlest_bit)
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{
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u32 r;
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r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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*idlest_reg = (__force void __iomem *)r;
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*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
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}
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const struct clkops clkops_omap3430es2_hsotgusb_wait = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
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.find_companion = omap2_clk_dflt_find_companion,
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};
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const struct clkops clkops_noncore_dpll_ops = {
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.enable = omap3_noncore_dpll_enable,
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.disable = omap3_noncore_dpll_disable,
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};
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int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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{
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/*
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* According to the 12-5 CDP code from TI, "Limitation 2.5"
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* on 3430ES1 prevents us from changing DPLL multipliers or dividers
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* on DPLL4.
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*/
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if (omap_rev() == OMAP3430_REV_ES1_0) {
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printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
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"silicon 'Limitation 2.5' on 3430ES1.\n");
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return -EINVAL;
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}
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return omap3_noncore_dpll_set_rate(clk, rate);
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}
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/* Common clock code */
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/*
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* Set clocks for bypass mode for reboot to work.
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*/
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void omap2_clk_prepare_for_reboot(void)
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{
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/* REVISIT: Not ready for 343x */
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#if 0
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u32 rate;
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if (vclk == NULL || sclk == NULL)
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return;
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rate = clk_get_rate(sclk);
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clk_set_rate(vclk, rate);
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#endif
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}
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void omap3_clk_lock_dpll5(void)
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{
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struct clk *dpll5_clk;
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struct clk *dpll5_m2_clk;
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dpll5_clk = clk_get(NULL, "dpll5_ck");
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clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_enable(dpll5_clk);
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/* Enable autoidle to allow it to enter low power bypass */
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omap3_dpll_allow_idle(dpll5_clk);
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/* Program dpll5_m2_clk divider for no division */
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dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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clk_enable(dpll5_m2_clk);
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clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_disable(dpll5_m2_clk);
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clk_disable(dpll5_clk);
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return;
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}
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/* REVISIT: Move this init stuff out into clock.c */
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/*
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* Switch the MPU rate if specified on cmdline.
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* We cannot do this early until cmdline is parsed.
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*/
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static int __init omap3xxx_clk_arch_init(void)
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{
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struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
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unsigned long osc_sys_rate;
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if (!cpu_is_omap34xx())
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return 0;
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if (!mpurate)
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return -EINVAL;
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/* XXX test these for success */
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dpll1_ck = clk_get(NULL, "dpll1_ck");
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arm_fck = clk_get(NULL, "arm_fck");
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core_ck = clk_get(NULL, "core_ck");
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osc_sys_ck = clk_get(NULL, "osc_sys_ck");
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/* REVISIT: not yet ready for 343x */
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if (clk_set_rate(dpll1_ck, mpurate))
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printk(KERN_ERR "*** Unable to set MPU rate\n");
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recalculate_root_clocks();
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osc_sys_rate = clk_get_rate(osc_sys_ck);
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pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(osc_sys_rate / 1000000),
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((osc_sys_rate / 100000) % 10),
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(clk_get_rate(core_ck) / 1000000),
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(clk_get_rate(arm_fck) / 1000000));
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calibrate_delay();
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return 0;
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}
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arch_initcall(omap3xxx_clk_arch_init);
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