James Liao dac5d67277 clk: mediatek: Allow changing PLL rate when it is off ... Some modules may need to change its clock rate before turn on it. So changing PLL's rate when it is off should be allowed. This patch removes PLL enabled check before set rate, so that PLLs can set new frequency even if they are off. On MT8173 for example, ARMPLL's enable bit can be controlled by other HW. That means ARMPLL may be turned on even if we (CPU / SW) set ARMPLL's enable bit as 0. In this case, SW may want and can still change ARMPLL's rate by changing its pcw and postdiv settings. But without this patch, new pcw setting will not be applied because its enable bit is 0. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Michael Turquette <mturuqette@baylibre.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2019-04-11 13:29:19 -07:00
..
clk-apmixed.c	clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS	2015-10-01 12:06:00 +08:00
clk-cpumux.c	clk: mediatek: Drop __init from mtk_clk_register_cpumuxes()	2018-11-30 00:39:19 -08:00
clk-cpumux.h	clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work	2017-06-19 19:02:43 -07:00
clk-gate.c	clk: mediatek: Add flags to mtk_gate	2019-02-26 09:53:39 -08:00
clk-gate.h	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt2701-aud.c	clk: mediatek: add audsys support for MT2701	2018-03-20 00:24:42 -07:00
clk-mt2701-bdp.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701-eth.c	clk: mediatek: add mt2701 ethernet reset	2017-04-21 19:20:33 -07:00
clk-mt2701-g3d.c	clk: mediatek: add g3dsys support for MT2701 and MT7623	2018-05-15 15:21:36 -07:00
clk-mt2701-hif.c	reset: mediatek: Add MT2701 reset driver	2016-11-08 15:59:51 -08:00
clk-mt2701-img.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701-mm.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701-vdec.c	clk: mediatek: Add MT2701 clock support	2016-11-08 15:59:49 -08:00
clk-mt2701.c	clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel	2019-02-25 09:19:33 -08:00
clk-mt2712-bdp.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-img.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-jpgdec.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-mfg.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-mm.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-vdec.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712-venc.c	clk: mediatek: Add MT2712 clock support	2017-11-02 01:02:53 -07:00
clk-mt2712.c	Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip' into clk-next	2019-03-08 10:34:22 -08:00
clk-mt6797-img.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797-mm.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797-vdec.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797-venc.c	clk: mediatek: add clk support for MT6797	2017-04-19 09:20:21 -07:00
clk-mt6797.c	clk: mediatek: Mark bus and DRAM related clocks as critical	2019-02-26 09:54:50 -08:00
clk-mt7622-aud.c	clk: mediatek: add devm_of_platform_populate() for MT7622 audsys	2018-03-20 00:24:33 -07:00
clk-mt7622-eth.c	clk: mediatek: add clock support for MT7622 SoC	2017-11-02 01:10:12 -07:00
clk-mt7622-hif.c	clk: mediatek: add clock support for MT7622 SoC	2017-11-02 01:10:12 -07:00
clk-mt7622.c	clk: mediatek: Drop more __init markings for driver probe	2018-11-30 00:39:39 -08:00
clk-mt7629-eth.c	clk: mediatek: add clock support for MT7629 SoC	2018-11-29 22:52:05 -08:00
clk-mt7629-hif.c	clk: mediatek: add clock support for MT7629 SoC	2018-11-29 22:52:05 -08:00
clk-mt7629.c	clk: mediatek: fix the PCIe MAC clock parent	2018-12-05 12:30:30 -08:00
clk-mt8135.c	clk: mediatek: Properly include clk.h	2015-07-20 10:53:09 -07:00
clk-mt8173.c	clk: mediatek: correct cpu clock name for MT8173 SoC	2019-02-26 10:17:40 -08:00
clk-mt8183-audio.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-cam.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-img.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-ipu0.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-ipu1.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-ipu_adl.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-ipu_conn.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-mfgcfg.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-mm.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-vdec.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183-venc.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mt8183.c	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
clk-mtk.c	Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next	2019-03-08 10:29:30 -08:00
clk-mtk.h	clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data	2019-04-11 13:20:16 -07:00
clk-mux.c	clk: mediatek: Add new clkmux register API	2019-04-11 13:12:40 -07:00
clk-mux.h	clk: mediatek: Add new clkmux register API	2019-04-11 13:12:40 -07:00
clk-pll.c	clk: mediatek: Allow changing PLL rate when it is off	2019-04-11 13:29:19 -07:00
Kconfig	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
Makefile	clk: mediatek: Add MT8183 clock support	2019-04-11 13:29:19 -07:00
reset.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00