![Benjamin Herrenschmidt](/assets/img/avatar_default.png)
This rewrites pretty much from scratch the handling of MMIO and PIO space allocations on powerpc64. The main goals are: - Get rid of imalloc and use more common code where possible - Simplify the current mess so that PIO space is allocated and mapped in a single place for PCI bridges - Handle allocation constraints of PIO for all bridges including hot plugged ones within the 2GB space reserved for IO ports, so that devices on hotplugged busses will now work with drivers that assume IO ports fit in an int. - Cleanup and separate tracking of the ISA space in the reserved low 64K of IO space. No ISA -> Nothing mapped there. I booted a cell blade with IDE on PIO and MMIO and a dual G5 so far, that's it :-) With this patch, all allocations are done using the code in mm/vmalloc.c, though we use the low level __get_vm_area with explicit start/stop constraints in order to manage separate areas for vmalloc/vmap, ioremap, and PCI IOs. This greatly simplifies a lot of things, as you can see in the diffstat of that patch :-) A new pair of functions pcibios_map/unmap_io_space() now replace all of the previous code that used to manipulate PCI IOs space. The allocation is done at mapping time, which is now called from scan_phb's, just before the devices are probed (instead of after, which is by itself a bug fix). The only other caller is the PCI hotplug code for hot adding PCI-PCI bridges (slots). imalloc is gone, as is the "sub-allocation" thing, but I do beleive that hotplug should still work in the sense that the space allocation is always done by the PHB, but if you unmap a child bus of this PHB (which seems to be possible), then the code should properly tear down all the HPTE mappings for that area of the PHB allocated IO space. I now always reserve the first 64K of IO space for the bridge with the ISA bus on it. I have moved the code for tracking ISA in a separate file which should also make it smarter if we ever are capable of hot unplugging or re-plugging an ISA bridge. This should have a side effect on platforms like powermac where VGA IOs will no longer work. This is done on purpose though as they would have worked semi-randomly before. The idea at this point is to isolate drivers that might need to access those and fix them by providing a proper function to obtain an offset to the legacy IOs of a given bus. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
298 lines
8.2 KiB
C
298 lines
8.2 KiB
C
/*
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* This file contains the routines for flushing entries from the
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* TLB and MMU hash table.
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*
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* Derived from arch/ppc64/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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* Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* Dave Engebretsen <engebret@us.ibm.com>
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* Rework for PPC64 port.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/bug.h>
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DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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/* This is declared as we are using the more or less generic
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* include/asm-powerpc/tlb.h file -- tgall
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*/
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
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DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
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unsigned long pte_freelist_forced_free;
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struct pte_freelist_batch
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{
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struct rcu_head rcu;
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unsigned int index;
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pgtable_free_t tables[0];
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};
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DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
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unsigned long pte_freelist_forced_free;
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#define PTE_FREELIST_SIZE \
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((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
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/ sizeof(pgtable_free_t))
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#ifdef CONFIG_SMP
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static void pte_free_smp_sync(void *arg)
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{
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/* Do nothing, just ensure we sync with all CPUs */
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}
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#endif
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/* This is only called when we are critically out of memory
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* (and fail to get a page in pte_free_tlb).
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*/
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static void pgtable_free_now(pgtable_free_t pgf)
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{
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pte_freelist_forced_free++;
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smp_call_function(pte_free_smp_sync, NULL, 0, 1);
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pgtable_free(pgf);
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}
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static void pte_free_rcu_callback(struct rcu_head *head)
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{
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struct pte_freelist_batch *batch =
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container_of(head, struct pte_freelist_batch, rcu);
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unsigned int i;
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for (i = 0; i < batch->index; i++)
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pgtable_free(batch->tables[i]);
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free_page((unsigned long)batch);
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}
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static void pte_free_submit(struct pte_freelist_batch *batch)
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{
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INIT_RCU_HEAD(&batch->rcu);
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call_rcu(&batch->rcu, pte_free_rcu_callback);
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}
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void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
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{
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/* This is safe since tlb_gather_mmu has disabled preemption */
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cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id());
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struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
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if (atomic_read(&tlb->mm->mm_users) < 2 ||
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cpus_equal(tlb->mm->cpu_vm_mask, local_cpumask)) {
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pgtable_free(pgf);
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return;
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}
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if (*batchp == NULL) {
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*batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
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if (*batchp == NULL) {
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pgtable_free_now(pgf);
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return;
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}
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(*batchp)->index = 0;
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}
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(*batchp)->tables[(*batchp)->index++] = pgf;
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if ((*batchp)->index == PTE_FREELIST_SIZE) {
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pte_free_submit(*batchp);
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*batchp = NULL;
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}
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}
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/*
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* A linux PTE was changed and the corresponding hash table entry
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* neesd to be flushed. This function will either perform the flush
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* immediately or will batch it up if the current CPU has an active
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* batch on it.
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*
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* Must be called from within some kind of spinlock/non-preempt region...
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*/
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void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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unsigned long vsid, vaddr;
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unsigned int psize;
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real_pte_t rpte;
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int i;
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i = batch->index;
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/* We mask the address for the base page size. Huge pages will
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* have applied their own masking already
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*/
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addr &= PAGE_MASK;
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/* Get page size (maybe move back to caller).
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*
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* NOTE: when using special 64K mappings in 4K environment like
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* for SPEs, we obtain the page size from the slice, which thus
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* must still exist (and thus the VMA not reused) at the time
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* of this call
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*/
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if (huge) {
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#ifdef CONFIG_HUGETLB_PAGE
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psize = mmu_huge_psize;
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#else
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BUG();
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psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
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#endif
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} else
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psize = pte_pagesize_index(mm, addr, pte);
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/* Build full vaddr */
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if (!is_kernel_addr(addr)) {
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vsid = get_vsid(mm->context.id, addr);
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WARN_ON(vsid == 0);
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} else
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vsid = get_kernel_vsid(addr);
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vaddr = (vsid << 28 ) | (addr & 0x0fffffff);
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rpte = __real_pte(__pte(pte), ptep);
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/*
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* Check if we have an active batch on this CPU. If not, just
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* flush now and return. For now, we don global invalidates
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* in that case, might be worth testing the mm cpu mask though
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* and decide to use local invalidates instead...
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*/
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if (!batch->active) {
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flush_hash_page(vaddr, rpte, psize, 0);
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return;
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}
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/*
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* This can happen when we are in the middle of a TLB batch and
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* we encounter memory pressure (eg copy_page_range when it tries
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* to allocate a new pte). If we have to reclaim memory and end
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* up scanning and resetting referenced bits then our batch context
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* will change mid stream.
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*
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* We also need to ensure only one page size is present in a given
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* batch
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*/
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if (i != 0 && (mm != batch->mm || batch->psize != psize)) {
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__flush_tlb_pending(batch);
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i = 0;
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}
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if (i == 0) {
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batch->mm = mm;
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batch->psize = psize;
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}
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batch->pte[i] = rpte;
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batch->vaddr[i] = vaddr;
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batch->index = ++i;
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if (i >= PPC64_TLB_BATCH_NR)
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__flush_tlb_pending(batch);
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}
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/*
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* This function is called when terminating an mmu batch or when a batch
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* is full. It will perform the flush of all the entries currently stored
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* in a batch.
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*
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* Must be called from within some kind of spinlock/non-preempt region...
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*/
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void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
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{
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cpumask_t tmp;
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int i, local = 0;
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i = batch->index;
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tmp = cpumask_of_cpu(smp_processor_id());
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if (cpus_equal(batch->mm->cpu_vm_mask, tmp))
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local = 1;
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if (i == 1)
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flush_hash_page(batch->vaddr[0], batch->pte[0],
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batch->psize, local);
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else
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flush_hash_range(i, local);
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batch->index = 0;
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}
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void pte_free_finish(void)
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{
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/* This is safe since tlb_gather_mmu has disabled preemption */
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struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
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if (*batchp == NULL)
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return;
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pte_free_submit(*batchp);
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*batchp = NULL;
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}
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/**
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* __flush_hash_table_range - Flush all HPTEs for a given address range
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* from the hash table (and the TLB). But keeps
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* the linux PTEs intact.
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*
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* @mm : mm_struct of the target address space (generally init_mm)
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* @start : starting address
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* @end : ending address (not included in the flush)
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*
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* This function is mostly to be used by some IO hotplug code in order
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* to remove all hash entries from a given address range used to map IO
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* space on a removed PCI-PCI bidge without tearing down the full mapping
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* since 64K pages may overlap with other bridges when using 64K pages
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* with 4K HW pages on IO space.
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*
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* Because of that usage pattern, it's only available with CONFIG_HOTPLUG
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* and is implemented for small size rather than speed.
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*/
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#ifdef CONFIG_HOTPLUG
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void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
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unsigned long end)
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{
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unsigned long flags;
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start = _ALIGN_DOWN(start, PAGE_SIZE);
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end = _ALIGN_UP(end, PAGE_SIZE);
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BUG_ON(!mm->pgd);
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/* Note: Normally, we should only ever use a batch within a
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* PTE locked section. This violates the rule, but will work
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* since we don't actually modify the PTEs, we just flush the
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* hash while leaving the PTEs intact (including their reference
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* to being hashed). This is not the most performance oriented
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* way to do things but is fine for our needs here.
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*/
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local_irq_save(flags);
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arch_enter_lazy_mmu_mode();
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for (; start < end; start += PAGE_SIZE) {
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pte_t *ptep = find_linux_pte(mm->pgd, start);
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unsigned long pte;
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if (ptep == NULL)
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continue;
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pte = pte_val(*ptep);
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if (!(pte & _PAGE_HASHPTE))
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continue;
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hpte_need_flush(mm, start, ptep, pte, 0);
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}
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arch_leave_lazy_mmu_mode();
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local_irq_restore(flags);
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}
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#endif /* CONFIG_HOTPLUG */
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