![Tony Lindgren](/assets/img/avatar_default.png)
We are currently only checking for the first entry in the table while
we should check them all. Usual no-idle-on-init is together with
no-reset-on-init, so this has gone unnoticed.
Fixes: 566a9b05e1
("bus: ti-sysc: Handle module quirks based dts
configuration")
Signed-off-by: Tony Lindgren <tony@atomide.com>
1015 lines
23 KiB
C
1015 lines
23 KiB
C
/*
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* ti-sysc.c - Texas Instruments sysc interconnect target driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/ti-sysc.h>
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#include <dt-bindings/bus/ti-sysc.h>
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enum sysc_registers {
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SYSC_REVISION,
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SYSC_SYSCONFIG,
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SYSC_SYSSTATUS,
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SYSC_MAX_REGS,
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};
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static const char * const reg_names[] = { "rev", "sysc", "syss", };
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enum sysc_clocks {
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SYSC_FCK,
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SYSC_ICK,
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SYSC_MAX_CLOCKS,
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};
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static const char * const clock_names[] = { "fck", "ick", };
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#define SYSC_IDLEMODE_MASK 3
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#define SYSC_CLOCKACTIVITY_MASK 3
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/**
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* struct sysc - TI sysc interconnect target module registers and capabilities
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* @dev: struct device pointer
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* @module_pa: physical address of the interconnect target module
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* @module_size: size of the interconnect target module
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* @module_va: virtual address of the interconnect target module
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* @offsets: register offsets from module base
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* @clocks: clocks used by the interconnect target module
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* @legacy_mode: configured for legacy mode if set
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* @cap: interconnect target module capabilities
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* @cfg: interconnect target module configuration
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* @name: name if available
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* @revision: interconnect target module revision
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*/
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struct sysc {
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struct device *dev;
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u64 module_pa;
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u32 module_size;
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void __iomem *module_va;
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int offsets[SYSC_MAX_REGS];
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struct clk *clocks[SYSC_MAX_CLOCKS];
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const char *legacy_mode;
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const struct sysc_capabilities *cap;
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struct sysc_config cfg;
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const char *name;
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u32 revision;
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};
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static u32 sysc_read(struct sysc *ddata, int offset)
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{
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if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
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u32 val;
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val = readw_relaxed(ddata->module_va + offset);
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val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
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return val;
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}
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return readl_relaxed(ddata->module_va + offset);
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}
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static u32 sysc_read_revision(struct sysc *ddata)
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{
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int offset = ddata->offsets[SYSC_REVISION];
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if (offset < 0)
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return 0;
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return sysc_read(ddata, offset);
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}
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static int sysc_get_one_clock(struct sysc *ddata,
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enum sysc_clocks index)
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{
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const char *name;
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int error;
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switch (index) {
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case SYSC_FCK:
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break;
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case SYSC_ICK:
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break;
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default:
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return -EINVAL;
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}
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name = clock_names[index];
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ddata->clocks[index] = devm_clk_get(ddata->dev, name);
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if (IS_ERR(ddata->clocks[index])) {
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if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
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return 0;
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dev_err(ddata->dev, "clock get error for %s: %li\n",
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name, PTR_ERR(ddata->clocks[index]));
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return PTR_ERR(ddata->clocks[index]);
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}
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error = clk_prepare(ddata->clocks[index]);
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if (error) {
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dev_err(ddata->dev, "clock prepare error for %s: %i\n",
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name, error);
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return error;
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}
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return 0;
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}
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static int sysc_get_clocks(struct sysc *ddata)
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{
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int i, error;
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if (ddata->legacy_mode)
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return 0;
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for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
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error = sysc_get_one_clock(ddata, i);
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if (error && error != -ENOENT)
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return error;
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}
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return 0;
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}
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/**
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* sysc_parse_and_check_child_range - parses module IO region from ranges
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* @ddata: device driver data
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*
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* In general we only need rev, syss, and sysc registers and not the whole
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* module range. But we do want the offsets for these registers from the
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* module base. This allows us to check them against the legacy hwmod
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* platform data. Let's also check the ranges are configured properly.
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*/
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static int sysc_parse_and_check_child_range(struct sysc *ddata)
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{
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struct device_node *np = ddata->dev->of_node;
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const __be32 *ranges;
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u32 nr_addr, nr_size;
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int len, error;
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ranges = of_get_property(np, "ranges", &len);
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if (!ranges) {
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dev_err(ddata->dev, "missing ranges for %pOF\n", np);
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return -ENOENT;
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}
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len /= sizeof(*ranges);
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if (len < 3) {
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dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
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return -EINVAL;
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}
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error = of_property_read_u32(np, "#address-cells", &nr_addr);
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if (error)
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return -ENOENT;
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error = of_property_read_u32(np, "#size-cells", &nr_size);
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if (error)
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return -ENOENT;
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if (nr_addr != 1 || nr_size != 1) {
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dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
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return -EINVAL;
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}
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ranges++;
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ddata->module_pa = of_translate_address(np, ranges++);
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ddata->module_size = be32_to_cpup(ranges);
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dev_dbg(ddata->dev, "interconnect target 0x%llx size 0x%x for %pOF\n",
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ddata->module_pa, ddata->module_size, np);
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return 0;
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}
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/**
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* sysc_check_one_child - check child configuration
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* @ddata: device driver data
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* @np: child device node
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*
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* Let's avoid messy situations where we have new interconnect target
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* node but children have "ti,hwmods". These belong to the interconnect
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* target node and are managed by this driver.
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*/
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static int sysc_check_one_child(struct sysc *ddata,
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struct device_node *np)
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{
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const char *name;
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name = of_get_property(np, "ti,hwmods", NULL);
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if (name)
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dev_warn(ddata->dev, "really a child ti,hwmods property?");
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return 0;
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}
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static int sysc_check_children(struct sysc *ddata)
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{
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struct device_node *child;
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int error;
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for_each_child_of_node(ddata->dev->of_node, child) {
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error = sysc_check_one_child(ddata, child);
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if (error)
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return error;
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}
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return 0;
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}
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/*
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* So far only I2C uses 16-bit read access with clockactivity with revision
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* in two registers with stride of 4. We can detect this based on the rev
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* register size to configure things far enough to be able to properly read
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* the revision register.
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*/
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static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
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{
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if (resource_size(res) == 8) {
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dev_dbg(ddata->dev,
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"enabling 16-bit and clockactivity quirks\n");
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ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
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}
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}
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/**
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* sysc_parse_one - parses the interconnect target module registers
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* @ddata: device driver data
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* @reg: register to parse
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*/
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static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
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{
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struct resource *res;
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const char *name;
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switch (reg) {
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case SYSC_REVISION:
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case SYSC_SYSCONFIG:
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case SYSC_SYSSTATUS:
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name = reg_names[reg];
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break;
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default:
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return -EINVAL;
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}
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res = platform_get_resource_byname(to_platform_device(ddata->dev),
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IORESOURCE_MEM, name);
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if (!res) {
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dev_dbg(ddata->dev, "has no %s register\n", name);
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ddata->offsets[reg] = -ENODEV;
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return 0;
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}
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ddata->offsets[reg] = res->start - ddata->module_pa;
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if (reg == SYSC_REVISION)
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sysc_check_quirk_16bit(ddata, res);
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return 0;
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}
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static int sysc_parse_registers(struct sysc *ddata)
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{
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int i, error;
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for (i = 0; i < SYSC_MAX_REGS; i++) {
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error = sysc_parse_one(ddata, i);
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if (error)
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return error;
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}
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return 0;
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}
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/**
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* sysc_check_registers - check for misconfigured register overlaps
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* @ddata: device driver data
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*/
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static int sysc_check_registers(struct sysc *ddata)
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{
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int i, j, nr_regs = 0, nr_matches = 0;
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for (i = 0; i < SYSC_MAX_REGS; i++) {
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if (ddata->offsets[i] < 0)
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continue;
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if (ddata->offsets[i] > (ddata->module_size - 4)) {
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dev_err(ddata->dev, "register outside module range");
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return -EINVAL;
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}
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for (j = 0; j < SYSC_MAX_REGS; j++) {
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if (ddata->offsets[j] < 0)
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continue;
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if (ddata->offsets[i] == ddata->offsets[j])
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nr_matches++;
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}
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nr_regs++;
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}
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if (nr_regs < 1) {
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dev_err(ddata->dev, "missing registers\n");
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return -EINVAL;
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}
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if (nr_matches > nr_regs) {
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dev_err(ddata->dev, "overlapping registers: (%i/%i)",
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nr_regs, nr_matches);
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return -EINVAL;
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}
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return 0;
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}
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/**
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* syc_ioremap - ioremap register space for the interconnect target module
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* @ddata: deviec driver data
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*
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* Note that the interconnect target module registers can be anywhere
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* within the first child device address space. For example, SGX has
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* them at offset 0x1fc00 in the 32MB module address space. We just
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* what we need around the interconnect target module registers.
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*/
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static int sysc_ioremap(struct sysc *ddata)
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{
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u32 size = 0;
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if (ddata->offsets[SYSC_SYSSTATUS] >= 0)
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size = ddata->offsets[SYSC_SYSSTATUS];
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else if (ddata->offsets[SYSC_SYSCONFIG] >= 0)
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size = ddata->offsets[SYSC_SYSCONFIG];
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else if (ddata->offsets[SYSC_REVISION] >= 0)
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size = ddata->offsets[SYSC_REVISION];
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else
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return -EINVAL;
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size &= 0xfff00;
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size += SZ_256;
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ddata->module_va = devm_ioremap(ddata->dev,
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ddata->module_pa,
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size);
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if (!ddata->module_va)
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return -EIO;
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return 0;
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}
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/**
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* sysc_map_and_check_registers - ioremap and check device registers
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* @ddata: device driver data
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*/
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static int sysc_map_and_check_registers(struct sysc *ddata)
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{
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int error;
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error = sysc_parse_and_check_child_range(ddata);
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if (error)
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return error;
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error = sysc_check_children(ddata);
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if (error)
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return error;
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error = sysc_parse_registers(ddata);
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if (error)
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return error;
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error = sysc_ioremap(ddata);
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if (error)
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return error;
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error = sysc_check_registers(ddata);
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if (error)
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return error;
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return 0;
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}
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/**
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* sysc_show_rev - read and show interconnect target module revision
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* @bufp: buffer to print the information to
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* @ddata: device driver data
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*/
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static int sysc_show_rev(char *bufp, struct sysc *ddata)
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{
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int len;
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if (ddata->offsets[SYSC_REVISION] < 0)
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return sprintf(bufp, ":NA");
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len = sprintf(bufp, ":%08x", ddata->revision);
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return len;
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}
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static int sysc_show_reg(struct sysc *ddata,
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char *bufp, enum sysc_registers reg)
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{
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if (ddata->offsets[reg] < 0)
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return sprintf(bufp, ":NA");
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return sprintf(bufp, ":%x", ddata->offsets[reg]);
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}
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/**
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* sysc_show_registers - show information about interconnect target module
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* @ddata: device driver data
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*/
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static void sysc_show_registers(struct sysc *ddata)
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{
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char buf[128];
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char *bufp = buf;
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int i;
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for (i = 0; i < SYSC_MAX_REGS; i++)
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bufp += sysc_show_reg(ddata, bufp, i);
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bufp += sysc_show_rev(bufp, ddata);
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dev_dbg(ddata->dev, "%llx:%x%s\n",
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ddata->module_pa, ddata->module_size,
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buf);
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}
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static int __maybe_unused sysc_runtime_suspend(struct device *dev)
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{
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struct sysc *ddata;
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int i;
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ddata = dev_get_drvdata(dev);
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if (ddata->legacy_mode)
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return 0;
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for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
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if (IS_ERR_OR_NULL(ddata->clocks[i]))
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continue;
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clk_disable(ddata->clocks[i]);
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}
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return 0;
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}
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static int __maybe_unused sysc_runtime_resume(struct device *dev)
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{
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struct sysc *ddata;
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int i, error;
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ddata = dev_get_drvdata(dev);
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if (ddata->legacy_mode)
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return 0;
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for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
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if (IS_ERR_OR_NULL(ddata->clocks[i]))
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continue;
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error = clk_enable(ddata->clocks[i]);
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if (error)
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return error;
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}
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return 0;
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}
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static const struct dev_pm_ops sysc_pm_ops = {
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SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
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sysc_runtime_resume,
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NULL)
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};
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/* At this point the module is configured enough to read the revision */
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static int sysc_init_module(struct sysc *ddata)
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{
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int error;
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error = pm_runtime_get_sync(ddata->dev);
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if (error < 0) {
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pm_runtime_put_noidle(ddata->dev);
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return 0;
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}
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ddata->revision = sysc_read_revision(ddata);
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pm_runtime_put_sync(ddata->dev);
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return 0;
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}
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static int sysc_init_sysc_mask(struct sysc *ddata)
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{
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struct device_node *np = ddata->dev->of_node;
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int error;
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u32 val;
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error = of_property_read_u32(np, "ti,sysc-mask", &val);
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if (error)
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return 0;
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if (val)
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ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
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else
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ddata->cfg.sysc_val = ddata->cap->sysc_mask;
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return 0;
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}
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static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
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const char *name)
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{
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struct device_node *np = ddata->dev->of_node;
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struct property *prop;
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const __be32 *p;
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u32 val;
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of_property_for_each_u32(np, name, prop, p, val) {
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if (val >= SYSC_NR_IDLEMODES) {
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dev_err(ddata->dev, "invalid idlemode: %i\n", val);
|
|
return -EINVAL;
|
|
}
|
|
*idlemodes |= (1 << val);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sysc_init_idlemodes(struct sysc *ddata)
|
|
{
|
|
int error;
|
|
|
|
error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
|
|
"ti,sysc-midle");
|
|
if (error)
|
|
return error;
|
|
|
|
error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
|
|
"ti,sysc-sidle");
|
|
if (error)
|
|
return error;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Only some devices on omap4 and later have SYSCONFIG reset done
|
|
* bit. We can detect this if there is no SYSSTATUS at all, or the
|
|
* SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
|
|
* have multiple bits for the child devices like OHCI and EHCI.
|
|
* Depends on SYSC being parsed first.
|
|
*/
|
|
static int sysc_init_syss_mask(struct sysc *ddata)
|
|
{
|
|
struct device_node *np = ddata->dev->of_node;
|
|
int error;
|
|
u32 val;
|
|
|
|
error = of_property_read_u32(np, "ti,syss-mask", &val);
|
|
if (error) {
|
|
if ((ddata->cap->type == TI_SYSC_OMAP4 ||
|
|
ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
|
|
(ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
|
|
ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
|
|
ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
|
|
|
|
ddata->cfg.syss_mask = val;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Device tree configured quirks */
|
|
struct sysc_dts_quirk {
|
|
const char *name;
|
|
u32 mask;
|
|
};
|
|
|
|
static const struct sysc_dts_quirk sysc_dts_quirks[] = {
|
|
{ .name = "ti,no-idle-on-init",
|
|
.mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
|
|
{ .name = "ti,no-reset-on-init",
|
|
.mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
|
|
};
|
|
|
|
static int sysc_init_dts_quirks(struct sysc *ddata)
|
|
{
|
|
struct device_node *np = ddata->dev->of_node;
|
|
const struct property *prop;
|
|
int i, len, error;
|
|
u32 val;
|
|
|
|
ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
|
|
prop = of_get_property(np, sysc_dts_quirks[i].name, &len);
|
|
if (!prop)
|
|
continue;
|
|
|
|
ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
|
|
}
|
|
|
|
error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
|
|
if (!error) {
|
|
if (val > 255) {
|
|
dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
|
|
val);
|
|
}
|
|
|
|
ddata->cfg.srst_udelay = (u8)val;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sysc_unprepare(struct sysc *ddata)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
|
|
if (!IS_ERR_OR_NULL(ddata->clocks[i]))
|
|
clk_unprepare(ddata->clocks[i]);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Common sysc register bits found on omap2, also known as type1
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap2 = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = 12,
|
|
.sidle_shift = 3,
|
|
.clkact_shift = 8,
|
|
.emufree_shift = 5,
|
|
.enwkup_shift = 2,
|
|
.srst_shift = 1,
|
|
.autoidle_shift = 0,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap2 = {
|
|
.type = TI_SYSC_OMAP2,
|
|
.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
|
|
SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE,
|
|
.regbits = &sysc_regbits_omap2,
|
|
};
|
|
|
|
/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
|
|
static const struct sysc_capabilities sysc_omap2_timer = {
|
|
.type = TI_SYSC_OMAP2_TIMER,
|
|
.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
|
|
SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE,
|
|
.regbits = &sysc_regbits_omap2,
|
|
.mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
|
|
};
|
|
|
|
/*
|
|
* SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
|
|
* with different sidle position
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap3_sham = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = -ENODEV,
|
|
.sidle_shift = 4,
|
|
.clkact_shift = -ENODEV,
|
|
.enwkup_shift = -ENODEV,
|
|
.srst_shift = 1,
|
|
.autoidle_shift = 0,
|
|
.emufree_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap3_sham = {
|
|
.type = TI_SYSC_OMAP3_SHAM,
|
|
.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
|
|
.regbits = &sysc_regbits_omap3_sham,
|
|
};
|
|
|
|
/*
|
|
* AES register bits found on omap3 and later, a variant of
|
|
* sysc_regbits_omap2 with different sidle position
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap3_aes = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = -ENODEV,
|
|
.sidle_shift = 6,
|
|
.clkact_shift = -ENODEV,
|
|
.enwkup_shift = -ENODEV,
|
|
.srst_shift = 1,
|
|
.autoidle_shift = 0,
|
|
.emufree_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap3_aes = {
|
|
.type = TI_SYSC_OMAP3_AES,
|
|
.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
|
|
.regbits = &sysc_regbits_omap3_aes,
|
|
};
|
|
|
|
/*
|
|
* Common sysc register bits found on omap4, also known as type2
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap4 = {
|
|
.dmadisable_shift = 16,
|
|
.midle_shift = 4,
|
|
.sidle_shift = 2,
|
|
.clkact_shift = -ENODEV,
|
|
.enwkup_shift = -ENODEV,
|
|
.emufree_shift = 1,
|
|
.srst_shift = 0,
|
|
.autoidle_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap4 = {
|
|
.type = TI_SYSC_OMAP4,
|
|
.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET,
|
|
.regbits = &sysc_regbits_omap4,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap4_timer = {
|
|
.type = TI_SYSC_OMAP4_TIMER,
|
|
.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET,
|
|
.regbits = &sysc_regbits_omap4,
|
|
};
|
|
|
|
/*
|
|
* Common sysc register bits found on omap4, also known as type3
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap4_simple = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = 2,
|
|
.sidle_shift = 0,
|
|
.clkact_shift = -ENODEV,
|
|
.enwkup_shift = -ENODEV,
|
|
.srst_shift = -ENODEV,
|
|
.emufree_shift = -ENODEV,
|
|
.autoidle_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap4_simple = {
|
|
.type = TI_SYSC_OMAP4_SIMPLE,
|
|
.regbits = &sysc_regbits_omap4_simple,
|
|
};
|
|
|
|
/*
|
|
* SmartReflex sysc found on omap34xx
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = -ENODEV,
|
|
.sidle_shift = -ENODEV,
|
|
.clkact_shift = 20,
|
|
.enwkup_shift = -ENODEV,
|
|
.srst_shift = -ENODEV,
|
|
.emufree_shift = -ENODEV,
|
|
.autoidle_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_34xx_sr = {
|
|
.type = TI_SYSC_OMAP34XX_SR,
|
|
.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
|
|
.regbits = &sysc_regbits_omap34xx_sr,
|
|
.mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED,
|
|
};
|
|
|
|
/*
|
|
* SmartReflex sysc found on omap36xx and later
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = -ENODEV,
|
|
.sidle_shift = 24,
|
|
.clkact_shift = -ENODEV,
|
|
.enwkup_shift = 26,
|
|
.srst_shift = -ENODEV,
|
|
.emufree_shift = -ENODEV,
|
|
.autoidle_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_36xx_sr = {
|
|
.type = TI_SYSC_OMAP36XX_SR,
|
|
.sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
|
|
.regbits = &sysc_regbits_omap36xx_sr,
|
|
.mod_quirks = SYSC_QUIRK_UNCACHED,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap4_sr = {
|
|
.type = TI_SYSC_OMAP4_SR,
|
|
.regbits = &sysc_regbits_omap36xx_sr,
|
|
};
|
|
|
|
/*
|
|
* McASP register bits found on omap4 and later
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = -ENODEV,
|
|
.sidle_shift = 0,
|
|
.clkact_shift = -ENODEV,
|
|
.enwkup_shift = -ENODEV,
|
|
.srst_shift = -ENODEV,
|
|
.emufree_shift = -ENODEV,
|
|
.autoidle_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap4_mcasp = {
|
|
.type = TI_SYSC_OMAP4_MCASP,
|
|
.regbits = &sysc_regbits_omap4_mcasp,
|
|
};
|
|
|
|
/*
|
|
* FS USB host found on omap4 and later
|
|
*/
|
|
static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
|
|
.dmadisable_shift = -ENODEV,
|
|
.midle_shift = -ENODEV,
|
|
.sidle_shift = 24,
|
|
.clkact_shift = -ENODEV,
|
|
.enwkup_shift = 26,
|
|
.srst_shift = -ENODEV,
|
|
.emufree_shift = -ENODEV,
|
|
.autoidle_shift = -ENODEV,
|
|
};
|
|
|
|
static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
|
|
.type = TI_SYSC_OMAP4_USB_HOST_FS,
|
|
.sysc_mask = SYSC_OMAP2_ENAWAKEUP,
|
|
.regbits = &sysc_regbits_omap4_usb_host_fs,
|
|
};
|
|
|
|
static int sysc_init_match(struct sysc *ddata)
|
|
{
|
|
const struct sysc_capabilities *cap;
|
|
|
|
cap = of_device_get_match_data(ddata->dev);
|
|
if (!cap)
|
|
return -EINVAL;
|
|
|
|
ddata->cap = cap;
|
|
if (ddata->cap)
|
|
ddata->cfg.quirks |= ddata->cap->mod_quirks;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sysc_probe(struct platform_device *pdev)
|
|
{
|
|
struct sysc *ddata;
|
|
int error;
|
|
|
|
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
|
|
if (!ddata)
|
|
return -ENOMEM;
|
|
|
|
ddata->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, ddata);
|
|
|
|
error = sysc_init_match(ddata);
|
|
if (error)
|
|
return error;
|
|
|
|
error = sysc_init_dts_quirks(ddata);
|
|
if (error)
|
|
goto unprepare;
|
|
|
|
error = sysc_get_clocks(ddata);
|
|
if (error)
|
|
return error;
|
|
|
|
error = sysc_map_and_check_registers(ddata);
|
|
if (error)
|
|
goto unprepare;
|
|
|
|
error = sysc_init_sysc_mask(ddata);
|
|
if (error)
|
|
goto unprepare;
|
|
|
|
error = sysc_init_idlemodes(ddata);
|
|
if (error)
|
|
goto unprepare;
|
|
|
|
error = sysc_init_syss_mask(ddata);
|
|
if (error)
|
|
goto unprepare;
|
|
|
|
pm_runtime_enable(ddata->dev);
|
|
|
|
error = sysc_init_module(ddata);
|
|
if (error)
|
|
goto unprepare;
|
|
|
|
error = pm_runtime_get_sync(ddata->dev);
|
|
if (error < 0) {
|
|
pm_runtime_put_noidle(ddata->dev);
|
|
pm_runtime_disable(ddata->dev);
|
|
goto unprepare;
|
|
}
|
|
|
|
pm_runtime_use_autosuspend(ddata->dev);
|
|
|
|
sysc_show_registers(ddata);
|
|
|
|
error = of_platform_populate(ddata->dev->of_node,
|
|
NULL, NULL, ddata->dev);
|
|
if (error)
|
|
goto err;
|
|
|
|
pm_runtime_mark_last_busy(ddata->dev);
|
|
pm_runtime_put_autosuspend(ddata->dev);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
unprepare:
|
|
sysc_unprepare(ddata);
|
|
|
|
return error;
|
|
}
|
|
|
|
static int sysc_remove(struct platform_device *pdev)
|
|
{
|
|
struct sysc *ddata = platform_get_drvdata(pdev);
|
|
int error;
|
|
|
|
error = pm_runtime_get_sync(ddata->dev);
|
|
if (error < 0) {
|
|
pm_runtime_put_noidle(ddata->dev);
|
|
pm_runtime_disable(ddata->dev);
|
|
goto unprepare;
|
|
}
|
|
|
|
of_platform_depopulate(&pdev->dev);
|
|
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
unprepare:
|
|
sysc_unprepare(ddata);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sysc_match[] = {
|
|
{ .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
|
|
{ .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
|
|
{ .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
|
|
{ .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
|
|
{ .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
|
|
{ .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
|
|
{ .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
|
|
{ .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
|
|
{ .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
|
|
{ .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
|
|
{ .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
|
|
{ .compatible = "ti,sysc-usb-host-fs",
|
|
.data = &sysc_omap4_usb_host_fs, },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sysc_match);
|
|
|
|
static struct platform_driver sysc_driver = {
|
|
.probe = sysc_probe,
|
|
.remove = sysc_remove,
|
|
.driver = {
|
|
.name = "ti-sysc",
|
|
.of_match_table = sysc_match,
|
|
.pm = &sysc_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(sysc_driver);
|
|
|
|
MODULE_DESCRIPTION("TI sysc interconnect target driver");
|
|
MODULE_LICENSE("GPL v2");
|