![Arvind Yadav](/assets/img/avatar_default.png)
The platform_get_irq() function returns negative if an error occurs. zero or positive number on success. platform_get_irq() error checking for zero is not correct. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
244 lines
5.9 KiB
C
244 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Faraday Technolog FTGPIO010 gpiochip and interrupt routines
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* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-gemini/gpio.c:
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* Based on plat-mxc/gpio.c:
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*/
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of_gpio.h>
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#include <linux/bitops.h>
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/* GPIO registers definition */
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#define GPIO_DATA_OUT 0x00
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#define GPIO_DATA_IN 0x04
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#define GPIO_DIR 0x08
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#define GPIO_DATA_SET 0x10
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#define GPIO_DATA_CLR 0x14
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#define GPIO_PULL_EN 0x18
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#define GPIO_PULL_TYPE 0x1C
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#define GPIO_INT_EN 0x20
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#define GPIO_INT_STAT 0x24
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#define GPIO_INT_MASK 0x2C
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#define GPIO_INT_CLR 0x30
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#define GPIO_INT_TYPE 0x34
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#define GPIO_INT_BOTH_EDGE 0x38
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#define GPIO_INT_LEVEL 0x3C
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#define GPIO_DEBOUNCE_EN 0x40
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#define GPIO_DEBOUNCE_PRESCALE 0x44
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/**
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* struct ftgpio_gpio - Gemini GPIO state container
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* @dev: containing device for this instance
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* @gc: gpiochip for this instance
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*/
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struct ftgpio_gpio {
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struct device *dev;
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struct gpio_chip gc;
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void __iomem *base;
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};
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static void ftgpio_gpio_ack_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
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}
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static void ftgpio_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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u32 val;
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val = readl(g->base + GPIO_INT_EN);
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val &= ~BIT(irqd_to_hwirq(d));
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writel(val, g->base + GPIO_INT_EN);
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}
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static void ftgpio_gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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u32 val;
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val = readl(g->base + GPIO_INT_EN);
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val |= BIT(irqd_to_hwirq(d));
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writel(val, g->base + GPIO_INT_EN);
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}
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static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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u32 mask = BIT(irqd_to_hwirq(d));
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u32 reg_both, reg_level, reg_type;
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reg_type = readl(g->base + GPIO_INT_TYPE);
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reg_level = readl(g->base + GPIO_INT_LEVEL);
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reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both |= mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both &= ~mask;
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reg_level &= ~mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both &= ~mask;
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reg_level |= mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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irq_set_handler_locked(d, handle_level_irq);
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reg_type |= mask;
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reg_level &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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irq_set_handler_locked(d, handle_level_irq);
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reg_type |= mask;
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reg_level |= mask;
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break;
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default:
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irq_set_handler_locked(d, handle_bad_irq);
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return -EINVAL;
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}
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writel(reg_type, g->base + GPIO_INT_TYPE);
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writel(reg_level, g->base + GPIO_INT_LEVEL);
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writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
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ftgpio_gpio_ack_irq(d);
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return 0;
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}
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static struct irq_chip ftgpio_gpio_irqchip = {
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.name = "FTGPIO010",
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.irq_ack = ftgpio_gpio_ack_irq,
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.irq_mask = ftgpio_gpio_mask_irq,
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.irq_unmask = ftgpio_gpio_unmask_irq,
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.irq_set_type = ftgpio_gpio_set_irq_type,
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};
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static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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int offset;
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unsigned long stat;
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chained_irq_enter(irqchip, desc);
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stat = readl(g->base + GPIO_INT_STAT);
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if (stat)
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for_each_set_bit(offset, &stat, gc->ngpio)
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generic_handle_irq(irq_find_mapping(gc->irq.domain,
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offset));
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chained_irq_exit(irqchip, desc);
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}
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static int ftgpio_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct ftgpio_gpio *g;
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int irq;
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int ret;
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g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
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if (!g)
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return -ENOMEM;
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g->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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g->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(g->base))
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return PTR_ERR(g->base);
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return irq ? irq : -EINVAL;
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ret = bgpio_init(&g->gc, dev, 4,
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g->base + GPIO_DATA_IN,
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g->base + GPIO_DATA_SET,
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g->base + GPIO_DATA_CLR,
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g->base + GPIO_DIR,
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NULL,
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0);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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return ret;
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}
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g->gc.label = "FTGPIO010";
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g->gc.base = -1;
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g->gc.parent = dev;
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g->gc.owner = THIS_MODULE;
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/* ngpio is set by bgpio_init() */
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ret = devm_gpiochip_add_data(dev, &g->gc, g);
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if (ret)
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return ret;
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/* Disable, unmask and clear all interrupts */
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writel(0x0, g->base + GPIO_INT_EN);
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writel(0x0, g->base + GPIO_INT_MASK);
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writel(~0x0, g->base + GPIO_INT_CLR);
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ret = gpiochip_irqchip_add(&g->gc, &ftgpio_gpio_irqchip,
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0, handle_bad_irq,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_info(dev, "could not add irqchip\n");
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return ret;
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}
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gpiochip_set_chained_irqchip(&g->gc, &ftgpio_gpio_irqchip,
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irq, ftgpio_gpio_irq_handler);
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dev_info(dev, "FTGPIO010 @%p registered\n", g->base);
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return 0;
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}
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static const struct of_device_id ftgpio_gpio_of_match[] = {
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{
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.compatible = "cortina,gemini-gpio",
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},
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{
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.compatible = "moxa,moxart-gpio",
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},
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{
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.compatible = "faraday,ftgpio010",
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},
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{},
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};
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static struct platform_driver ftgpio_gpio_driver = {
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.driver = {
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.name = "ftgpio010-gpio",
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.of_match_table = of_match_ptr(ftgpio_gpio_of_match),
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},
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.probe = ftgpio_gpio_probe,
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};
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builtin_platform_driver(ftgpio_gpio_driver);
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