![Markus Mayer](/assets/img/avatar_default.png)
The DCPU can now send message data in two ways: - via the data RAM, as before (this is now message type 0) - via the message RAM (this is message type 1) In order to support both methods, we check the message type of the response (bits 31:28) and then treat the offset (bits 27:0) accordingly. Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
769 lines
19 KiB
C
769 lines
19 KiB
C
/*
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* DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
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*
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* Copyright (c) 2017 Broadcom
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*
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* Released under the GPLv2 only.
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* SPDX-License-Identifier: GPL-2.0
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*/
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/*
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* This driver provides access to the DPFE interface of Broadcom STB SoCs.
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* The firmware running on the DCPU inside the DDR PHY can provide current
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* information about the system's RAM, for instance the DRAM refresh rate.
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* This can be used as an indirect indicator for the DRAM's temperature.
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* Slower refresh rate means cooler RAM, higher refresh rate means hotter
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* RAM.
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*
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* Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
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* already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
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*
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* Note regarding the loading of the firmware image: we use be32_to_cpu()
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* and le_32_to_cpu(), so we can support the following four cases:
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* - LE kernel + LE firmware image (the most common case)
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* - LE kernel + BE firmware image
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* - BE kernel + LE firmware image
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* - BE kernel + BE firmware image
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*
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* The DPCU always runs in big endian mode. The firwmare image, however, can
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* be in either format. Also, communication between host CPU and DCPU is
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* always in little endian.
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*/
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#define DRVNAME "brcmstb-dpfe"
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#define FIRMWARE_NAME "dpfe.bin"
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/* DCPU register offsets */
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#define REG_DCPU_RESET 0x0
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#define REG_TO_DCPU_MBOX 0x10
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#define REG_TO_HOST_MBOX 0x14
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/* Macros to process offsets returned by the DCPU */
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#define DRAM_MSG_ADDR_OFFSET 0x0
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#define DRAM_MSG_TYPE_OFFSET 0x1c
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#define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
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#define DRAM_MSG_TYPE_MASK ((1UL << \
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(BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
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/* Message RAM */
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#define DCPU_MSG_RAM_START 0x100
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#define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32))
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/* DRAM Info Offsets & Masks */
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#define DRAM_INFO_INTERVAL 0x0
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#define DRAM_INFO_MR4 0x4
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#define DRAM_INFO_ERROR 0x8
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#define DRAM_INFO_MR4_MASK 0xff
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/* DRAM MR4 Offsets & Masks */
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#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */
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#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */
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#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */
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#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */
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#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */
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#define DRAM_MR4_REFRESH_MASK 0x7
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#define DRAM_MR4_SR_ABORT_MASK 0x1
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#define DRAM_MR4_PPRE_MASK 0x1
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#define DRAM_MR4_TH_OFFS_MASK 0x3
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#define DRAM_MR4_TUF_MASK 0x1
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/* DRAM Vendor Offsets & Masks */
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#define DRAM_VENDOR_MR5 0x0
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#define DRAM_VENDOR_MR6 0x4
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#define DRAM_VENDOR_MR7 0x8
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#define DRAM_VENDOR_MR8 0xc
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#define DRAM_VENDOR_ERROR 0x10
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#define DRAM_VENDOR_MASK 0xff
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/* Reset register bits & masks */
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#define DCPU_RESET_SHIFT 0x0
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#define DCPU_RESET_MASK 0x1
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#define DCPU_CLK_DISABLE_SHIFT 0x2
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/* DCPU return codes */
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#define DCPU_RET_ERROR_BIT BIT(31)
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#define DCPU_RET_SUCCESS 0x1
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#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0))
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#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1))
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#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2))
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#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3))
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/* This error code is not firmware defined and only used in the driver. */
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#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4))
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/* Firmware magic */
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#define DPFE_BE_MAGIC 0xfe1010fe
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#define DPFE_LE_MAGIC 0xfe0101fe
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/* Error codes */
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#define ERR_INVALID_MAGIC -1
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#define ERR_INVALID_SIZE -2
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#define ERR_INVALID_CHKSUM -3
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/* Message types */
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#define DPFE_MSG_TYPE_COMMAND 1
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#define DPFE_MSG_TYPE_RESPONSE 2
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#define DELAY_LOOP_MAX 200000
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enum dpfe_msg_fields {
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MSG_HEADER,
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MSG_COMMAND,
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MSG_ARG_COUNT,
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MSG_ARG0,
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MSG_CHKSUM,
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MSG_FIELD_MAX /* Last entry */
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};
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enum dpfe_commands {
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DPFE_CMD_GET_INFO,
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DPFE_CMD_GET_REFRESH,
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DPFE_CMD_GET_VENDOR,
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DPFE_CMD_MAX /* Last entry */
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};
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struct dpfe_msg {
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u32 header;
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u32 command;
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u32 arg_count;
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u32 arg0;
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u32 chksum; /* This is the sum of all other entries. */
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};
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/*
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* Format of the binary firmware file:
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*
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* entry
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* 0 header
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* value: 0xfe0101fe <== little endian
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* 0xfe1010fe <== big endian
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* 1 sequence:
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* [31:16] total segments on this build
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* [15:0] this segment sequence.
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* 2 FW version
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* 3 IMEM byte size
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* 4 DMEM byte size
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* IMEM
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* DMEM
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* last checksum ==> sum of everything
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*/
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struct dpfe_firmware_header {
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u32 magic;
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u32 sequence;
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u32 version;
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u32 imem_size;
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u32 dmem_size;
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};
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/* Things we only need during initialization. */
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struct init_data {
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unsigned int dmem_len;
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unsigned int imem_len;
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unsigned int chksum;
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bool is_big_endian;
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};
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/* Things we need for as long as we are active. */
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struct private_data {
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void __iomem *regs;
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void __iomem *dmem;
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void __iomem *imem;
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struct device *dev;
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unsigned int index;
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struct mutex lock;
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};
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static const char *error_text[] = {
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"Success", "Header code incorrect", "Unknown command or argument",
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"Incorrect checksum", "Malformed command", "Timed out",
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};
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/* List of supported firmware commands */
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static const u32 dpfe_commands[DPFE_CMD_MAX][MSG_FIELD_MAX] = {
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[DPFE_CMD_GET_INFO] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 1,
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[MSG_ARG_COUNT] = 1,
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[MSG_ARG0] = 1,
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[MSG_CHKSUM] = 4,
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},
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[DPFE_CMD_GET_REFRESH] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 2,
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[MSG_ARG_COUNT] = 1,
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[MSG_ARG0] = 1,
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[MSG_CHKSUM] = 5,
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},
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[DPFE_CMD_GET_VENDOR] = {
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[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
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[MSG_COMMAND] = 2,
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[MSG_ARG_COUNT] = 1,
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[MSG_ARG0] = 2,
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[MSG_CHKSUM] = 6,
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},
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};
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static bool is_dcpu_enabled(void __iomem *regs)
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{
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u32 val;
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val = readl_relaxed(regs + REG_DCPU_RESET);
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return !(val & DCPU_RESET_MASK);
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}
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static void __disable_dcpu(void __iomem *regs)
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{
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u32 val;
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if (!is_dcpu_enabled(regs))
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return;
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/* Put DCPU in reset if it's running. */
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val = readl_relaxed(regs + REG_DCPU_RESET);
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val |= (1 << DCPU_RESET_SHIFT);
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writel_relaxed(val, regs + REG_DCPU_RESET);
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}
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static void __enable_dcpu(void __iomem *regs)
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{
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u32 val;
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/* Clear mailbox registers. */
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writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
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writel_relaxed(0, regs + REG_TO_HOST_MBOX);
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/* Disable DCPU clock gating */
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val = readl_relaxed(regs + REG_DCPU_RESET);
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val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
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writel_relaxed(val, regs + REG_DCPU_RESET);
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/* Take DCPU out of reset */
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val = readl_relaxed(regs + REG_DCPU_RESET);
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val &= ~(1 << DCPU_RESET_SHIFT);
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writel_relaxed(val, regs + REG_DCPU_RESET);
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}
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static unsigned int get_msg_chksum(const u32 msg[])
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{
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unsigned int sum = 0;
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unsigned int i;
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/* Don't include the last field in the checksum. */
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for (i = 0; i < MSG_FIELD_MAX - 1; i++)
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sum += msg[i];
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return sum;
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}
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static void __iomem *get_msg_ptr(struct private_data *priv, u32 response,
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char *buf, ssize_t *size)
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{
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unsigned int msg_type;
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unsigned int offset;
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void __iomem *ptr = NULL;
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msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
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offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
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/*
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* msg_type == 1: the offset is relative to the message RAM
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* msg_type == 0: the offset is relative to the data RAM (this is the
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* previous way of passing data)
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* msg_type is anything else: there's critical hardware problem
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*/
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switch (msg_type) {
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case 1:
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ptr = priv->regs + DCPU_MSG_RAM_START + offset;
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break;
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case 0:
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ptr = priv->dmem + offset;
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break;
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default:
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dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
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response);
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if (buf && size)
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*size = sprintf(buf,
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"FATAL: communication error with DCPU\n");
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}
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return ptr;
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}
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static int __send_command(struct private_data *priv, unsigned int cmd,
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u32 result[])
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{
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const u32 *msg = dpfe_commands[cmd];
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void __iomem *regs = priv->regs;
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unsigned int i, chksum;
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int ret = 0;
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u32 resp;
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if (cmd >= DPFE_CMD_MAX)
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return -1;
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mutex_lock(&priv->lock);
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/* Write command and arguments to message area */
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for (i = 0; i < MSG_FIELD_MAX; i++)
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writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
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/* Tell DCPU there is a command waiting */
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writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
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/* Wait for DCPU to process the command */
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for (i = 0; i < DELAY_LOOP_MAX; i++) {
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/* Read response code */
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resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
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if (resp > 0)
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break;
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udelay(5);
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}
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if (i == DELAY_LOOP_MAX) {
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resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
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ret = -ffs(resp);
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} else {
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/* Read response data */
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for (i = 0; i < MSG_FIELD_MAX; i++)
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result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
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}
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/* Tell DCPU we are done */
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writel_relaxed(0, regs + REG_TO_HOST_MBOX);
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mutex_unlock(&priv->lock);
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if (ret)
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return ret;
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/* Verify response */
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chksum = get_msg_chksum(result);
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if (chksum != result[MSG_CHKSUM])
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resp = DCPU_RET_ERR_CHKSUM;
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if (resp != DCPU_RET_SUCCESS) {
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resp &= ~DCPU_RET_ERROR_BIT;
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ret = -ffs(resp);
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}
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return ret;
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}
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/* Ensure that the firmware file loaded meets all the requirements. */
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static int __verify_firmware(struct init_data *init,
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const struct firmware *fw)
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{
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const struct dpfe_firmware_header *header = (void *)fw->data;
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unsigned int dmem_size, imem_size, total_size;
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bool is_big_endian = false;
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const u32 *chksum_ptr;
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if (header->magic == DPFE_BE_MAGIC)
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is_big_endian = true;
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else if (header->magic != DPFE_LE_MAGIC)
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return ERR_INVALID_MAGIC;
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if (is_big_endian) {
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dmem_size = be32_to_cpu(header->dmem_size);
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imem_size = be32_to_cpu(header->imem_size);
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} else {
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dmem_size = le32_to_cpu(header->dmem_size);
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imem_size = le32_to_cpu(header->imem_size);
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}
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/* Data and instruction sections are 32 bit words. */
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if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
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return ERR_INVALID_SIZE;
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/*
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* The header + the data section + the instruction section + the
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* checksum must be equal to the total firmware size.
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*/
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total_size = dmem_size + imem_size + sizeof(*header) +
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sizeof(*chksum_ptr);
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if (total_size != fw->size)
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return ERR_INVALID_SIZE;
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/* The checksum comes at the very end. */
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chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
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init->is_big_endian = is_big_endian;
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init->dmem_len = dmem_size;
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init->imem_len = imem_size;
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init->chksum = (is_big_endian)
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? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
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return 0;
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}
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/* Verify checksum by reading back the firmware from co-processor RAM. */
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static int __verify_fw_checksum(struct init_data *init,
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struct private_data *priv,
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const struct dpfe_firmware_header *header,
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u32 checksum)
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{
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u32 magic, sequence, version, sum;
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u32 __iomem *dmem = priv->dmem;
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u32 __iomem *imem = priv->imem;
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unsigned int i;
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if (init->is_big_endian) {
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magic = be32_to_cpu(header->magic);
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sequence = be32_to_cpu(header->sequence);
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version = be32_to_cpu(header->version);
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} else {
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magic = le32_to_cpu(header->magic);
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sequence = le32_to_cpu(header->sequence);
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version = le32_to_cpu(header->version);
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}
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sum = magic + sequence + version + init->dmem_len + init->imem_len;
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for (i = 0; i < init->dmem_len / sizeof(u32); i++)
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sum += readl_relaxed(dmem + i);
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for (i = 0; i < init->imem_len / sizeof(u32); i++)
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sum += readl_relaxed(imem + i);
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return (sum == checksum) ? 0 : -1;
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}
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static int __write_firmware(u32 __iomem *mem, const u32 *fw,
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unsigned int size, bool is_big_endian)
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{
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unsigned int i;
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/* Convert size to 32-bit words. */
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size /= sizeof(u32);
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/* It is recommended to clear the firmware area first. */
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for (i = 0; i < size; i++)
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writel_relaxed(0, mem + i);
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/* Now copy it. */
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if (is_big_endian) {
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for (i = 0; i < size; i++)
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writel_relaxed(be32_to_cpu(fw[i]), mem + i);
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} else {
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for (i = 0; i < size; i++)
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writel_relaxed(le32_to_cpu(fw[i]), mem + i);
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}
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return 0;
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}
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static int brcmstb_dpfe_download_firmware(struct platform_device *pdev,
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struct init_data *init)
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{
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const struct dpfe_firmware_header *header;
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unsigned int dmem_size, imem_size;
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struct device *dev = &pdev->dev;
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bool is_big_endian = false;
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struct private_data *priv;
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const struct firmware *fw;
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const u32 *dmem, *imem;
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const void *fw_blob;
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int ret;
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priv = platform_get_drvdata(pdev);
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/*
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* Skip downloading the firmware if the DCPU is already running and
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* responding to commands.
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*/
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if (is_dcpu_enabled(priv->regs)) {
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u32 response[MSG_FIELD_MAX];
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ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
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if (!ret)
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return 0;
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}
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ret = request_firmware(&fw, FIRMWARE_NAME, dev);
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/* request_firmware() prints its own error messages. */
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if (ret)
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return ret;
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ret = __verify_firmware(init, fw);
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if (ret)
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return -EFAULT;
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__disable_dcpu(priv->regs);
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|
|
is_big_endian = init->is_big_endian;
|
|
dmem_size = init->dmem_len;
|
|
imem_size = init->imem_len;
|
|
|
|
/* At the beginning of the firmware blob is a header. */
|
|
header = (struct dpfe_firmware_header *)fw->data;
|
|
/* Void pointer to the beginning of the actual firmware. */
|
|
fw_blob = fw->data + sizeof(*header);
|
|
/* IMEM comes right after the header. */
|
|
imem = fw_blob;
|
|
/* DMEM follows after IMEM. */
|
|
dmem = fw_blob + imem_size;
|
|
|
|
ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
|
|
if (ret)
|
|
return ret;
|
|
ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = __verify_fw_checksum(init, priv, header, init->chksum);
|
|
if (ret)
|
|
return ret;
|
|
|
|
__enable_dcpu(priv->regs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t generic_show(unsigned int command, u32 response[],
|
|
struct device *dev, char *buf)
|
|
{
|
|
struct private_data *priv;
|
|
int ret;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
if (!priv)
|
|
return sprintf(buf, "ERROR: driver private data not set\n");
|
|
|
|
ret = __send_command(priv, command, response);
|
|
if (ret < 0)
|
|
return sprintf(buf, "ERROR: %s\n", error_text[-ret]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
|
|
char *buf)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
unsigned int info;
|
|
ssize_t ret;
|
|
|
|
ret = generic_show(DPFE_CMD_GET_INFO, response, dev, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info = response[MSG_ARG0];
|
|
|
|
return sprintf(buf, "%u.%u.%u.%u\n",
|
|
(info >> 24) & 0xff,
|
|
(info >> 16) & 0xff,
|
|
(info >> 8) & 0xff,
|
|
info & 0xff);
|
|
}
|
|
|
|
static ssize_t show_refresh(struct device *dev,
|
|
struct device_attribute *devattr, char *buf)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
void __iomem *info;
|
|
struct private_data *priv;
|
|
u8 refresh, sr_abort, ppre, thermal_offs, tuf;
|
|
u32 mr4;
|
|
ssize_t ret;
|
|
|
|
ret = generic_show(DPFE_CMD_GET_REFRESH, response, dev, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
|
|
info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
|
|
if (!info)
|
|
return ret;
|
|
|
|
mr4 = readl_relaxed(info + DRAM_INFO_MR4) & DRAM_INFO_MR4_MASK;
|
|
|
|
refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
|
|
sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
|
|
ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
|
|
thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
|
|
tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
|
|
|
|
return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
|
|
readl_relaxed(info + DRAM_INFO_INTERVAL),
|
|
refresh, sr_abort, ppre, thermal_offs, tuf,
|
|
readl_relaxed(info + DRAM_INFO_ERROR));
|
|
}
|
|
|
|
static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
struct private_data *priv;
|
|
void __iomem *info;
|
|
unsigned long val;
|
|
int ret;
|
|
|
|
if (kstrtoul(buf, 0, &val) < 0)
|
|
return -EINVAL;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
|
|
ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
|
|
if (!info)
|
|
return -EIO;
|
|
|
|
writel_relaxed(val, info + DRAM_INFO_INTERVAL);
|
|
|
|
return count;
|
|
}
|
|
|
|
static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
|
|
char *buf)
|
|
{
|
|
u32 response[MSG_FIELD_MAX];
|
|
struct private_data *priv;
|
|
void __iomem *info;
|
|
ssize_t ret;
|
|
|
|
ret = generic_show(DPFE_CMD_GET_VENDOR, response, dev, buf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
priv = dev_get_drvdata(dev);
|
|
|
|
info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
|
|
if (!info)
|
|
return ret;
|
|
|
|
return sprintf(buf, "%#x %#x %#x %#x %#x\n",
|
|
readl_relaxed(info + DRAM_VENDOR_MR5) & DRAM_VENDOR_MASK,
|
|
readl_relaxed(info + DRAM_VENDOR_MR6) & DRAM_VENDOR_MASK,
|
|
readl_relaxed(info + DRAM_VENDOR_MR7) & DRAM_VENDOR_MASK,
|
|
readl_relaxed(info + DRAM_VENDOR_MR8) & DRAM_VENDOR_MASK,
|
|
readl_relaxed(info + DRAM_VENDOR_ERROR) &
|
|
DRAM_VENDOR_MASK);
|
|
}
|
|
|
|
static int brcmstb_dpfe_resume(struct platform_device *pdev)
|
|
{
|
|
struct init_data init;
|
|
|
|
return brcmstb_dpfe_download_firmware(pdev, &init);
|
|
}
|
|
|
|
static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
|
|
static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
|
|
static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
|
|
static struct attribute *dpfe_attrs[] = {
|
|
&dev_attr_dpfe_info.attr,
|
|
&dev_attr_dpfe_refresh.attr,
|
|
&dev_attr_dpfe_vendor.attr,
|
|
NULL
|
|
};
|
|
ATTRIBUTE_GROUPS(dpfe);
|
|
|
|
static int brcmstb_dpfe_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct private_data *priv;
|
|
struct device *dpfe_dev;
|
|
struct init_data init;
|
|
struct resource *res;
|
|
u32 index;
|
|
int ret;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
mutex_init(&priv->lock);
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
/* Cell index is optional; default to 0 if not present. */
|
|
ret = of_property_read_u32(dev->of_node, "cell-index", &index);
|
|
if (ret)
|
|
index = 0;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
|
|
priv->regs = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(priv->regs)) {
|
|
dev_err(dev, "couldn't map DCPU registers\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
|
|
priv->dmem = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(priv->dmem)) {
|
|
dev_err(dev, "Couldn't map DCPU data memory\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
|
|
priv->imem = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(priv->imem)) {
|
|
dev_err(dev, "Couldn't map DCPU instruction memory\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
ret = brcmstb_dpfe_download_firmware(pdev, &init);
|
|
if (ret)
|
|
goto err;
|
|
|
|
dpfe_dev = devm_kzalloc(dev, sizeof(*dpfe_dev), GFP_KERNEL);
|
|
if (!dpfe_dev) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
priv->dev = dpfe_dev;
|
|
priv->index = index;
|
|
|
|
dpfe_dev->parent = dev;
|
|
dpfe_dev->groups = dpfe_groups;
|
|
dpfe_dev->of_node = dev->of_node;
|
|
dev_set_drvdata(dpfe_dev, priv);
|
|
dev_set_name(dpfe_dev, "dpfe%u", index);
|
|
|
|
ret = device_register(dpfe_dev);
|
|
if (ret)
|
|
goto err;
|
|
|
|
dev_info(dev, "registered.\n");
|
|
|
|
return 0;
|
|
|
|
err:
|
|
dev_err(dev, "failed to initialize -- error %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id brcmstb_dpfe_of_match[] = {
|
|
{ .compatible = "brcm,dpfe-cpu", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
|
|
|
|
static struct platform_driver brcmstb_dpfe_driver = {
|
|
.driver = {
|
|
.name = DRVNAME,
|
|
.of_match_table = brcmstb_dpfe_of_match,
|
|
},
|
|
.probe = brcmstb_dpfe_probe,
|
|
.resume = brcmstb_dpfe_resume,
|
|
};
|
|
|
|
module_platform_driver(brcmstb_dpfe_driver);
|
|
|
|
MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
|
|
MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
|
|
MODULE_LICENSE("GPL");
|