![Kishon Vijay Abraham I](/assets/img/avatar_default.png)
pci_disable_msi() throws a Kernel BUG if the driver has successfully requested an IRQ and not released it. Fix it here by freeing IRQs before invoking pci_disable_msi(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
650 lines
16 KiB
C
650 lines
16 KiB
C
/**
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* Host side test driver to test endpoint functionality
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/crc32.h>
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <uapi/linux/pcitest.h>
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#define DRV_MODULE_NAME "pci-endpoint-test"
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#define PCI_ENDPOINT_TEST_MAGIC 0x0
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#define PCI_ENDPOINT_TEST_COMMAND 0x4
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#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
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#define COMMAND_RAISE_MSI_IRQ BIT(1)
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#define MSI_NUMBER_SHIFT 2
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/* 6 bits for MSI number */
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#define COMMAND_READ BIT(8)
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#define COMMAND_WRITE BIT(9)
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#define COMMAND_COPY BIT(10)
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#define PCI_ENDPOINT_TEST_STATUS 0x8
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#define STATUS_READ_SUCCESS BIT(0)
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#define STATUS_READ_FAIL BIT(1)
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#define STATUS_WRITE_SUCCESS BIT(2)
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#define STATUS_WRITE_FAIL BIT(3)
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#define STATUS_COPY_SUCCESS BIT(4)
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#define STATUS_COPY_FAIL BIT(5)
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#define STATUS_IRQ_RAISED BIT(6)
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#define STATUS_SRC_ADDR_INVALID BIT(7)
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#define STATUS_DST_ADDR_INVALID BIT(8)
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#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
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#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
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#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
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#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
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#define PCI_ENDPOINT_TEST_SIZE 0x1c
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#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
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static DEFINE_IDA(pci_endpoint_test_ida);
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#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
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miscdev)
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static bool no_msi;
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module_param(no_msi, bool, 0444);
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MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
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enum pci_barno {
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BAR_0,
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BAR_1,
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BAR_2,
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BAR_3,
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BAR_4,
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BAR_5,
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};
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struct pci_endpoint_test {
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struct pci_dev *pdev;
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void __iomem *base;
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void __iomem *bar[6];
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struct completion irq_raised;
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int last_irq;
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int num_irqs;
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/* mutex to protect the ioctls */
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struct mutex mutex;
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struct miscdevice miscdev;
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enum pci_barno test_reg_bar;
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size_t alignment;
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};
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struct pci_endpoint_test_data {
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enum pci_barno test_reg_bar;
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size_t alignment;
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bool no_msi;
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};
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static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
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u32 offset)
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{
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return readl(test->base + offset);
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}
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static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
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u32 offset, u32 value)
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{
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writel(value, test->base + offset);
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}
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static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
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int bar, int offset)
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{
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return readl(test->bar[bar] + offset);
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}
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static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
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int bar, u32 offset, u32 value)
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{
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writel(value, test->bar[bar] + offset);
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}
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static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
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{
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struct pci_endpoint_test *test = dev_id;
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u32 reg;
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reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
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if (reg & STATUS_IRQ_RAISED) {
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test->last_irq = irq;
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complete(&test->irq_raised);
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reg &= ~STATUS_IRQ_RAISED;
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}
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
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reg);
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return IRQ_HANDLED;
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}
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static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
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enum pci_barno barno)
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{
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int j;
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u32 val;
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int size;
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struct pci_dev *pdev = test->pdev;
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if (!test->bar[barno])
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return false;
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size = pci_resource_len(pdev, barno);
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if (barno == test->test_reg_bar)
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size = 0x4;
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for (j = 0; j < size; j += 4)
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pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
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for (j = 0; j < size; j += 4) {
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val = pci_endpoint_test_bar_readl(test, barno, j);
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if (val != 0xA0A0A0A0)
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return false;
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}
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return true;
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}
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static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
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{
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u32 val;
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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COMMAND_RAISE_LEGACY_IRQ);
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val = wait_for_completion_timeout(&test->irq_raised,
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msecs_to_jiffies(1000));
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if (!val)
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return false;
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return true;
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}
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static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
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u8 msi_num)
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{
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u32 val;
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struct pci_dev *pdev = test->pdev;
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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msi_num << MSI_NUMBER_SHIFT |
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COMMAND_RAISE_MSI_IRQ);
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val = wait_for_completion_timeout(&test->irq_raised,
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msecs_to_jiffies(1000));
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if (!val)
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return false;
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if (test->last_irq - pdev->irq == msi_num - 1)
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return true;
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return false;
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}
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static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
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{
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bool ret = false;
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void *src_addr;
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void *dst_addr;
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dma_addr_t src_phys_addr;
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dma_addr_t dst_phys_addr;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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void *orig_src_addr;
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dma_addr_t orig_src_phys_addr;
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void *orig_dst_addr;
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dma_addr_t orig_dst_phys_addr;
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size_t offset;
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size_t alignment = test->alignment;
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u32 src_crc32;
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u32 dst_crc32;
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if (size > SIZE_MAX - alignment)
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goto err;
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orig_src_addr = dma_alloc_coherent(dev, size + alignment,
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&orig_src_phys_addr, GFP_KERNEL);
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if (!orig_src_addr) {
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dev_err(dev, "failed to allocate source buffer\n");
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ret = false;
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goto err;
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}
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if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
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src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
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offset = src_phys_addr - orig_src_phys_addr;
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src_addr = orig_src_addr + offset;
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} else {
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src_phys_addr = orig_src_phys_addr;
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src_addr = orig_src_addr;
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}
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
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lower_32_bits(src_phys_addr));
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
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upper_32_bits(src_phys_addr));
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get_random_bytes(src_addr, size);
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src_crc32 = crc32_le(~0, src_addr, size);
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orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
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&orig_dst_phys_addr, GFP_KERNEL);
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if (!orig_dst_addr) {
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dev_err(dev, "failed to allocate destination address\n");
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ret = false;
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goto err_orig_src_addr;
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}
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if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
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dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
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offset = dst_phys_addr - orig_dst_phys_addr;
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dst_addr = orig_dst_addr + offset;
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} else {
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dst_phys_addr = orig_dst_phys_addr;
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dst_addr = orig_dst_addr;
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}
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
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lower_32_bits(dst_phys_addr));
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
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upper_32_bits(dst_phys_addr));
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
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size);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
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wait_for_completion(&test->irq_raised);
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dst_crc32 = crc32_le(~0, dst_addr, size);
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if (dst_crc32 == src_crc32)
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ret = true;
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dma_free_coherent(dev, size + alignment, orig_dst_addr,
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orig_dst_phys_addr);
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err_orig_src_addr:
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dma_free_coherent(dev, size + alignment, orig_src_addr,
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orig_src_phys_addr);
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err:
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return ret;
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}
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static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
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{
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bool ret = false;
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u32 reg;
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void *addr;
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dma_addr_t phys_addr;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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void *orig_addr;
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dma_addr_t orig_phys_addr;
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size_t offset;
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size_t alignment = test->alignment;
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u32 crc32;
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if (size > SIZE_MAX - alignment)
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goto err;
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orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
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GFP_KERNEL);
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if (!orig_addr) {
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dev_err(dev, "failed to allocate address\n");
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ret = false;
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goto err;
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}
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if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
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phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
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offset = phys_addr - orig_phys_addr;
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addr = orig_addr + offset;
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} else {
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phys_addr = orig_phys_addr;
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addr = orig_addr;
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}
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get_random_bytes(addr, size);
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crc32 = crc32_le(~0, addr, size);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
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crc32);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
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lower_32_bits(phys_addr));
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
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upper_32_bits(phys_addr));
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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1 << MSI_NUMBER_SHIFT | COMMAND_READ);
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wait_for_completion(&test->irq_raised);
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reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
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if (reg & STATUS_READ_SUCCESS)
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ret = true;
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dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
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err:
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return ret;
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}
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static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
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{
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bool ret = false;
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void *addr;
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dma_addr_t phys_addr;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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void *orig_addr;
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dma_addr_t orig_phys_addr;
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size_t offset;
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size_t alignment = test->alignment;
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u32 crc32;
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if (size > SIZE_MAX - alignment)
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goto err;
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orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
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GFP_KERNEL);
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if (!orig_addr) {
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dev_err(dev, "failed to allocate destination address\n");
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ret = false;
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goto err;
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}
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if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
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phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
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offset = phys_addr - orig_phys_addr;
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addr = orig_addr + offset;
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} else {
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phys_addr = orig_phys_addr;
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addr = orig_addr;
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}
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
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lower_32_bits(phys_addr));
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
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upper_32_bits(phys_addr));
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
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wait_for_completion(&test->irq_raised);
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crc32 = crc32_le(~0, addr, size);
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if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
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ret = true;
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dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
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err:
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return ret;
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}
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static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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int ret = -EINVAL;
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enum pci_barno bar;
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struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
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mutex_lock(&test->mutex);
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switch (cmd) {
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case PCITEST_BAR:
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bar = arg;
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if (bar < 0 || bar > 5)
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goto ret;
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ret = pci_endpoint_test_bar(test, bar);
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break;
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case PCITEST_LEGACY_IRQ:
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ret = pci_endpoint_test_legacy_irq(test);
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break;
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case PCITEST_MSI:
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ret = pci_endpoint_test_msi_irq(test, arg);
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break;
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case PCITEST_WRITE:
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ret = pci_endpoint_test_write(test, arg);
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break;
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case PCITEST_READ:
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ret = pci_endpoint_test_read(test, arg);
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break;
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case PCITEST_COPY:
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ret = pci_endpoint_test_copy(test, arg);
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break;
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}
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ret:
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mutex_unlock(&test->mutex);
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return ret;
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}
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static const struct file_operations pci_endpoint_test_fops = {
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.owner = THIS_MODULE,
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.unlocked_ioctl = pci_endpoint_test_ioctl,
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};
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static int pci_endpoint_test_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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int i;
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int err;
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int irq = 0;
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int id;
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char name[20];
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enum pci_barno bar;
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void __iomem *base;
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struct device *dev = &pdev->dev;
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struct pci_endpoint_test *test;
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struct pci_endpoint_test_data *data;
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enum pci_barno test_reg_bar = BAR_0;
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struct miscdevice *misc_device;
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if (pci_is_bridge(pdev))
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return -ENODEV;
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test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
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if (!test)
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return -ENOMEM;
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test->test_reg_bar = 0;
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test->alignment = 0;
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test->pdev = pdev;
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data = (struct pci_endpoint_test_data *)ent->driver_data;
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if (data) {
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test_reg_bar = data->test_reg_bar;
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test->alignment = data->alignment;
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no_msi = data->no_msi;
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}
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init_completion(&test->irq_raised);
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mutex_init(&test->mutex);
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err = pci_enable_device(pdev);
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if (err) {
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dev_err(dev, "Cannot enable PCI device\n");
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return err;
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}
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err = pci_request_regions(pdev, DRV_MODULE_NAME);
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if (err) {
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dev_err(dev, "Cannot obtain PCI resources\n");
|
|
goto err_disable_pdev;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
if (!no_msi) {
|
|
irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
|
|
if (irq < 0)
|
|
dev_err(dev, "failed to get MSI interrupts\n");
|
|
test->num_irqs = irq;
|
|
}
|
|
|
|
err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
|
|
IRQF_SHARED, DRV_MODULE_NAME, test);
|
|
if (err) {
|
|
dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
|
|
goto err_disable_msi;
|
|
}
|
|
|
|
for (i = 1; i < irq; i++) {
|
|
err = devm_request_irq(dev, pdev->irq + i,
|
|
pci_endpoint_test_irqhandler,
|
|
IRQF_SHARED, DRV_MODULE_NAME, test);
|
|
if (err)
|
|
dev_err(dev, "failed to request IRQ %d for MSI %d\n",
|
|
pdev->irq + i, i + 1);
|
|
}
|
|
|
|
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
|
base = pci_ioremap_bar(pdev, bar);
|
|
if (!base) {
|
|
dev_err(dev, "failed to read BAR%d\n", bar);
|
|
WARN_ON(bar == test_reg_bar);
|
|
}
|
|
test->bar[bar] = base;
|
|
}
|
|
|
|
test->base = test->bar[test_reg_bar];
|
|
if (!test->base) {
|
|
err = -ENOMEM;
|
|
dev_err(dev, "Cannot perform PCI test without BAR%d\n",
|
|
test_reg_bar);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
pci_set_drvdata(pdev, test);
|
|
|
|
id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
|
|
if (id < 0) {
|
|
err = id;
|
|
dev_err(dev, "unable to get id\n");
|
|
goto err_iounmap;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
|
|
misc_device = &test->miscdev;
|
|
misc_device->minor = MISC_DYNAMIC_MINOR;
|
|
misc_device->name = kstrdup(name, GFP_KERNEL);
|
|
if (!misc_device->name) {
|
|
err = -ENOMEM;
|
|
goto err_ida_remove;
|
|
}
|
|
misc_device->fops = &pci_endpoint_test_fops,
|
|
|
|
err = misc_register(misc_device);
|
|
if (err) {
|
|
dev_err(dev, "failed to register device\n");
|
|
goto err_kfree_name;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_kfree_name:
|
|
kfree(misc_device->name);
|
|
|
|
err_ida_remove:
|
|
ida_simple_remove(&pci_endpoint_test_ida, id);
|
|
|
|
err_iounmap:
|
|
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
|
if (test->bar[bar])
|
|
pci_iounmap(pdev, test->bar[bar]);
|
|
}
|
|
|
|
for (i = 0; i < irq; i++)
|
|
devm_free_irq(dev, pdev->irq + i, test);
|
|
|
|
err_disable_msi:
|
|
pci_disable_msi(pdev);
|
|
pci_release_regions(pdev);
|
|
|
|
err_disable_pdev:
|
|
pci_disable_device(pdev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void pci_endpoint_test_remove(struct pci_dev *pdev)
|
|
{
|
|
int id;
|
|
int i;
|
|
enum pci_barno bar;
|
|
struct pci_endpoint_test *test = pci_get_drvdata(pdev);
|
|
struct miscdevice *misc_device = &test->miscdev;
|
|
|
|
if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
|
|
return;
|
|
if (id < 0)
|
|
return;
|
|
|
|
misc_deregister(&test->miscdev);
|
|
kfree(misc_device->name);
|
|
ida_simple_remove(&pci_endpoint_test_ida, id);
|
|
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
|
if (test->bar[bar])
|
|
pci_iounmap(pdev, test->bar[bar]);
|
|
}
|
|
for (i = 0; i < test->num_irqs; i++)
|
|
devm_free_irq(&pdev->dev, pdev->irq + i, test);
|
|
pci_disable_msi(pdev);
|
|
pci_release_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
static const struct pci_device_id pci_endpoint_test_tbl[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
|
|
|
|
static struct pci_driver pci_endpoint_test_driver = {
|
|
.name = DRV_MODULE_NAME,
|
|
.id_table = pci_endpoint_test_tbl,
|
|
.probe = pci_endpoint_test_probe,
|
|
.remove = pci_endpoint_test_remove,
|
|
};
|
|
module_pci_driver(pci_endpoint_test_driver);
|
|
|
|
MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
|
|
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|