![Stephen Boyd](/assets/img/avatar_default.png)
Convert this driver to use irqdomains so that the PMIC's child devices can be converted to devicetree. Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
513 lines
13 KiB
C
513 lines
13 KiB
C
/*
|
|
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 and
|
|
* only version 2 as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#define pr_fmt(fmt) "%s: " fmt, __func__
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/irqchip/chained_irq.h>
|
|
#include <linux/irq.h>
|
|
#include <linux/irqdomain.h>
|
|
#include <linux/module.h>
|
|
#include <linux/platform_device.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/err.h>
|
|
#include <linux/ssbi.h>
|
|
#include <linux/of_platform.h>
|
|
#include <linux/mfd/core.h>
|
|
#include <linux/mfd/pm8xxx/core.h>
|
|
|
|
#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
|
|
|
|
#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
|
|
#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
|
|
#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
|
|
#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
|
|
#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
|
|
#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
|
|
#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
|
|
#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
|
|
#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
|
|
|
|
#define PM_IRQF_LVL_SEL 0x01 /* level select */
|
|
#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
|
|
#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
|
|
#define PM_IRQF_CLR 0x08 /* clear interrupt */
|
|
#define PM_IRQF_BITS_MASK 0x70
|
|
#define PM_IRQF_BITS_SHIFT 4
|
|
#define PM_IRQF_WRITE 0x80
|
|
|
|
#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
|
|
PM_IRQF_MASK_RE)
|
|
|
|
#define REG_HWREV 0x002 /* PMIC4 revision */
|
|
#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
|
|
|
|
#define PM8921_NR_IRQS 256
|
|
|
|
struct pm_irq_chip {
|
|
struct device *dev;
|
|
spinlock_t pm_irq_lock;
|
|
struct irq_domain *irqdomain;
|
|
unsigned int num_irqs;
|
|
unsigned int num_blocks;
|
|
unsigned int num_masters;
|
|
u8 config[0];
|
|
};
|
|
|
|
struct pm8921 {
|
|
struct device *dev;
|
|
struct pm_irq_chip *irq_chip;
|
|
};
|
|
|
|
static int pm8xxx_read_root_irq(const struct pm_irq_chip *chip, u8 *rp)
|
|
{
|
|
return pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_ROOT, rp);
|
|
}
|
|
|
|
static int pm8xxx_read_master_irq(const struct pm_irq_chip *chip, u8 m, u8 *bp)
|
|
{
|
|
return pm8xxx_readb(chip->dev,
|
|
SSBI_REG_ADDR_IRQ_M_STATUS1 + m, bp);
|
|
}
|
|
|
|
static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, u8 bp, u8 *ip)
|
|
{
|
|
int rc;
|
|
|
|
spin_lock(&chip->pm_irq_lock);
|
|
rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
|
|
if (rc) {
|
|
pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
|
|
goto bail;
|
|
}
|
|
|
|
rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
|
|
if (rc)
|
|
pr_err("Failed Reading Status rc=%d\n", rc);
|
|
bail:
|
|
spin_unlock(&chip->pm_irq_lock);
|
|
return rc;
|
|
}
|
|
|
|
static int pm8xxx_config_irq(struct pm_irq_chip *chip, u8 bp, u8 cp)
|
|
{
|
|
int rc;
|
|
|
|
spin_lock(&chip->pm_irq_lock);
|
|
rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
|
|
if (rc) {
|
|
pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
|
|
goto bail;
|
|
}
|
|
|
|
cp |= PM_IRQF_WRITE;
|
|
rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_CONFIG, cp);
|
|
if (rc)
|
|
pr_err("Failed Configuring IRQ rc=%d\n", rc);
|
|
bail:
|
|
spin_unlock(&chip->pm_irq_lock);
|
|
return rc;
|
|
}
|
|
|
|
static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
|
|
{
|
|
int pmirq, irq, i, ret = 0;
|
|
u8 bits;
|
|
|
|
ret = pm8xxx_read_block_irq(chip, block, &bits);
|
|
if (ret) {
|
|
pr_err("Failed reading %d block ret=%d", block, ret);
|
|
return ret;
|
|
}
|
|
if (!bits) {
|
|
pr_err("block bit set in master but no irqs: %d", block);
|
|
return 0;
|
|
}
|
|
|
|
/* Check IRQ bits */
|
|
for (i = 0; i < 8; i++) {
|
|
if (bits & (1 << i)) {
|
|
pmirq = block * 8 + i;
|
|
irq = irq_find_mapping(chip->irqdomain, pmirq);
|
|
generic_handle_irq(irq);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
|
|
{
|
|
u8 blockbits;
|
|
int block_number, i, ret = 0;
|
|
|
|
ret = pm8xxx_read_master_irq(chip, master, &blockbits);
|
|
if (ret) {
|
|
pr_err("Failed to read master %d ret=%d\n", master, ret);
|
|
return ret;
|
|
}
|
|
if (!blockbits) {
|
|
pr_err("master bit set in root but no blocks: %d", master);
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0; i < 8; i++)
|
|
if (blockbits & (1 << i)) {
|
|
block_number = master * 8 + i; /* block # */
|
|
ret |= pm8xxx_irq_block_handler(chip, block_number);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
|
|
struct irq_chip *irq_chip = irq_desc_get_chip(desc);
|
|
u8 root;
|
|
int i, ret, masters = 0;
|
|
|
|
chained_irq_enter(irq_chip, desc);
|
|
|
|
ret = pm8xxx_read_root_irq(chip, &root);
|
|
if (ret) {
|
|
pr_err("Can't read root status ret=%d\n", ret);
|
|
return;
|
|
}
|
|
|
|
/* on pm8xxx series masters start from bit 1 of the root */
|
|
masters = root >> 1;
|
|
|
|
/* Read allowed masters for blocks. */
|
|
for (i = 0; i < chip->num_masters; i++)
|
|
if (masters & (1 << i))
|
|
pm8xxx_irq_master_handler(chip, i);
|
|
|
|
chained_irq_exit(irq_chip, desc);
|
|
}
|
|
|
|
static void pm8xxx_irq_mask_ack(struct irq_data *d)
|
|
{
|
|
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
|
|
unsigned int pmirq = irqd_to_hwirq(d);
|
|
int irq_bit;
|
|
u8 block, config;
|
|
|
|
block = pmirq / 8;
|
|
irq_bit = pmirq % 8;
|
|
|
|
config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
|
|
pm8xxx_config_irq(chip, block, config);
|
|
}
|
|
|
|
static void pm8xxx_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
|
|
unsigned int pmirq = irqd_to_hwirq(d);
|
|
int irq_bit;
|
|
u8 block, config;
|
|
|
|
block = pmirq / 8;
|
|
irq_bit = pmirq % 8;
|
|
|
|
config = chip->config[pmirq];
|
|
pm8xxx_config_irq(chip, block, config);
|
|
}
|
|
|
|
static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
|
{
|
|
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
|
|
unsigned int pmirq = irqd_to_hwirq(d);
|
|
int irq_bit;
|
|
u8 block, config;
|
|
|
|
block = pmirq / 8;
|
|
irq_bit = pmirq % 8;
|
|
|
|
chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
|
|
| PM_IRQF_MASK_ALL;
|
|
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
|
|
if (flow_type & IRQF_TRIGGER_RISING)
|
|
chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
|
|
if (flow_type & IRQF_TRIGGER_FALLING)
|
|
chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
|
|
} else {
|
|
chip->config[pmirq] |= PM_IRQF_LVL_SEL;
|
|
|
|
if (flow_type & IRQF_TRIGGER_HIGH)
|
|
chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
|
|
else
|
|
chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
|
|
}
|
|
|
|
config = chip->config[pmirq] | PM_IRQF_CLR;
|
|
return pm8xxx_config_irq(chip, block, config);
|
|
}
|
|
|
|
static int pm8xxx_irq_set_wake(struct irq_data *d, unsigned int on)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static struct irq_chip pm8xxx_irq_chip = {
|
|
.name = "pm8xxx",
|
|
.irq_mask_ack = pm8xxx_irq_mask_ack,
|
|
.irq_unmask = pm8xxx_irq_unmask,
|
|
.irq_set_type = pm8xxx_irq_set_type,
|
|
.irq_set_wake = pm8xxx_irq_set_wake,
|
|
.flags = IRQCHIP_MASK_ON_SUSPEND,
|
|
};
|
|
|
|
/**
|
|
* pm8xxx_get_irq_stat - get the status of the irq line
|
|
* @chip: pointer to identify a pmic irq controller
|
|
* @irq: the irq number
|
|
*
|
|
* The pm8xxx gpio and mpp rely on the interrupt block to read
|
|
* the values on their pins. This function is to facilitate reading
|
|
* the status of a gpio or an mpp line. The caller has to convert the
|
|
* gpio number to irq number.
|
|
*
|
|
* RETURNS:
|
|
* an int indicating the value read on that line
|
|
*/
|
|
static int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
|
|
{
|
|
int pmirq, rc;
|
|
u8 block, bits, bit;
|
|
unsigned long flags;
|
|
struct irq_data *irq_data = irq_get_irq_data(irq);
|
|
|
|
pmirq = irq_data->hwirq;
|
|
|
|
block = pmirq / 8;
|
|
bit = pmirq % 8;
|
|
|
|
spin_lock_irqsave(&chip->pm_irq_lock, flags);
|
|
|
|
rc = pm8xxx_writeb(chip->dev, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
|
|
if (rc) {
|
|
pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
|
|
irq, pmirq, block, rc);
|
|
goto bail_out;
|
|
}
|
|
|
|
rc = pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
|
|
if (rc) {
|
|
pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
|
|
irq, pmirq, block, rc);
|
|
goto bail_out;
|
|
}
|
|
|
|
rc = (bits & (1 << bit)) ? 1 : 0;
|
|
|
|
bail_out:
|
|
spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static struct lock_class_key pm8xxx_irq_lock_class;
|
|
|
|
static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
struct pm_irq_chip *chip = d->host_data;
|
|
|
|
irq_set_lockdep_class(irq, &pm8xxx_irq_lock_class);
|
|
irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
|
|
irq_set_chip_data(irq, chip);
|
|
#ifdef CONFIG_ARM
|
|
set_irq_flags(irq, IRQF_VALID);
|
|
#else
|
|
irq_set_noprobe(irq);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
|
|
.xlate = irq_domain_xlate_twocell,
|
|
.map = pm8xxx_irq_domain_map,
|
|
};
|
|
|
|
static int pm8921_readb(const struct device *dev, u16 addr, u8 *val)
|
|
{
|
|
const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
|
|
const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
|
|
|
|
return ssbi_read(pmic->dev->parent, addr, val, 1);
|
|
}
|
|
|
|
static int pm8921_writeb(const struct device *dev, u16 addr, u8 val)
|
|
{
|
|
const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
|
|
const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
|
|
|
|
return ssbi_write(pmic->dev->parent, addr, &val, 1);
|
|
}
|
|
|
|
static int pm8921_read_buf(const struct device *dev, u16 addr, u8 *buf,
|
|
int cnt)
|
|
{
|
|
const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
|
|
const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
|
|
|
|
return ssbi_read(pmic->dev->parent, addr, buf, cnt);
|
|
}
|
|
|
|
static int pm8921_write_buf(const struct device *dev, u16 addr, u8 *buf,
|
|
int cnt)
|
|
{
|
|
const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
|
|
const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
|
|
|
|
return ssbi_write(pmic->dev->parent, addr, buf, cnt);
|
|
}
|
|
|
|
static int pm8921_read_irq_stat(const struct device *dev, int irq)
|
|
{
|
|
const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
|
|
const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
|
|
|
|
return pm8xxx_get_irq_stat(pmic->irq_chip, irq);
|
|
}
|
|
|
|
static struct pm8xxx_drvdata pm8921_drvdata = {
|
|
.pmic_readb = pm8921_readb,
|
|
.pmic_writeb = pm8921_writeb,
|
|
.pmic_read_buf = pm8921_read_buf,
|
|
.pmic_write_buf = pm8921_write_buf,
|
|
.pmic_read_irq_stat = pm8921_read_irq_stat,
|
|
};
|
|
|
|
static int pm8921_probe(struct platform_device *pdev)
|
|
{
|
|
struct pm8921 *pmic;
|
|
int rc;
|
|
u8 val;
|
|
unsigned int irq;
|
|
u32 rev;
|
|
struct pm_irq_chip *chip;
|
|
unsigned int nirqs = PM8921_NR_IRQS;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
pmic = devm_kzalloc(&pdev->dev, sizeof(struct pm8921), GFP_KERNEL);
|
|
if (!pmic) {
|
|
pr_err("Cannot alloc pm8921 struct\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Read PMIC chip revision */
|
|
rc = ssbi_read(pdev->dev.parent, REG_HWREV, &val, sizeof(val));
|
|
if (rc) {
|
|
pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
|
|
return rc;
|
|
}
|
|
pr_info("PMIC revision 1: %02X\n", val);
|
|
rev = val;
|
|
|
|
/* Read PMIC chip revision 2 */
|
|
rc = ssbi_read(pdev->dev.parent, REG_HWREV_2, &val, sizeof(val));
|
|
if (rc) {
|
|
pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
|
|
REG_HWREV_2, rc);
|
|
return rc;
|
|
}
|
|
pr_info("PMIC revision 2: %02X\n", val);
|
|
rev |= val << BITS_PER_BYTE;
|
|
|
|
pmic->dev = &pdev->dev;
|
|
pm8921_drvdata.pm_chip_data = pmic;
|
|
platform_set_drvdata(pdev, &pm8921_drvdata);
|
|
|
|
chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
|
|
sizeof(chip->config[0]) * nirqs,
|
|
GFP_KERNEL);
|
|
if (!chip)
|
|
return -ENOMEM;
|
|
|
|
pmic->irq_chip = chip;
|
|
chip->dev = &pdev->dev;
|
|
chip->num_irqs = nirqs;
|
|
chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
|
|
chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
|
|
spin_lock_init(&chip->pm_irq_lock);
|
|
|
|
chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
|
|
&pm8xxx_irq_domain_ops,
|
|
chip);
|
|
if (!chip->irqdomain)
|
|
return -ENODEV;
|
|
|
|
irq_set_handler_data(irq, chip);
|
|
irq_set_chained_handler(irq, pm8xxx_irq_handler);
|
|
irq_set_irq_wake(irq, 1);
|
|
|
|
rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
|
|
if (rc) {
|
|
irq_set_chained_handler(irq, NULL);
|
|
irq_set_handler_data(irq, NULL);
|
|
irq_domain_remove(chip->irqdomain);
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int pm8921_remove_child(struct device *dev, void *unused)
|
|
{
|
|
platform_device_unregister(to_platform_device(dev));
|
|
return 0;
|
|
}
|
|
|
|
static int pm8921_remove(struct platform_device *pdev)
|
|
{
|
|
int irq = platform_get_irq(pdev, 0);
|
|
struct pm8921 *pmic = pm8921_drvdata.pm_chip_data;
|
|
struct pm_irq_chip *chip = pmic->irq_chip;
|
|
|
|
device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
|
|
irq_set_chained_handler(irq, NULL);
|
|
irq_set_handler_data(irq, NULL);
|
|
irq_domain_remove(chip->irqdomain);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver pm8921_driver = {
|
|
.probe = pm8921_probe,
|
|
.remove = pm8921_remove,
|
|
.driver = {
|
|
.name = "pm8921-core",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init pm8921_init(void)
|
|
{
|
|
return platform_driver_register(&pm8921_driver);
|
|
}
|
|
subsys_initcall(pm8921_init);
|
|
|
|
static void __exit pm8921_exit(void)
|
|
{
|
|
platform_driver_unregister(&pm8921_driver);
|
|
}
|
|
module_exit(pm8921_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("PMIC 8921 core driver");
|
|
MODULE_VERSION("1.0");
|
|
MODULE_ALIAS("platform:pm8921-core");
|