![Ondrej Zary](/assets/img/avatar_default.png)
Unify struct ft1000_info between ft1000-usb and ft1000-pcmcia and move it to common ft1000.h. Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Marek Belisko <marek.belisko@open-nandra.com> Review-by: Marek Belisko <marek.belisko@open-nandra.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
288 lines
11 KiB
C
288 lines
11 KiB
C
/*
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* Common structures and definitions for FT1000 Flarion Flash OFDM PCMCIA and USB devices
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*
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* Originally copyright (c) 2002 Flarion Technologies
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*
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*/
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#define DSPVERSZ 4
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#define HWSERNUMSZ 16
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#define SKUSZ 20
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#define EUISZ 8
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#define MODESZ 2
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#define CALVERSZ 2
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#define CALDATESZ 6
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#define ELECTRABUZZ_ID 0 /* ASIC ID for Electrabuzz */
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#define MAGNEMITE_ID 0x1a01 /* ASIC ID for Magnemite */
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/* MEMORY MAP common to both ELECTRABUZZ and MAGNEMITE */
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#define FT1000_REG_DPRAM_ADDR 0x000E /* DPADR - Dual Port Ram Indirect Address Register */
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#define FT1000_REG_SUP_CTRL 0x0020 /* HCTR - Host Control Register */
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#define FT1000_REG_SUP_STAT 0x0022 /* HSTAT - Host Status Register */
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#define FT1000_REG_RESET 0x0024 /* HCTR - Host Control Register */
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#define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status Register */
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#define FT1000_REG_SUP_IMASK 0x0028 /* HIMASK - Host Interrupt Mask */
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#define FT1000_REG_DOORBELL 0x002a /* DBELL - Door Bell Register */
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#define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification Number */
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/* MEMORY MAP FOR ELECTRABUZZ ASIC */
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#define FT1000_REG_UFIFO_STAT 0x0000 /* UFSR - Uplink FIFO status register */
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#define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning register */
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#define FT1000_REG_UFIFO_MID 0x0004 /* UFMR - Uplink FIFO middle register */
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#define FT1000_REG_UFIFO_END 0x0006 /* UFER - Uplink FIFO end register */
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#define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status register */
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#define FT1000_REG_DFIFO 0x000A /* DFR - Downlink FIFO Register */
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#define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect Data Register */
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#define FT1000_REG_WATERMARK 0x0010 /* WMARK - Watermark Register */
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/* MEMORY MAP FOR MAGNEMITE */
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#define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data Register (32-bits) */
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#define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data Register low-word (16-bits) */
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#define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register high-word (16-bits) */
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#define FT1000_REG_MAG_UFER 0x0004 /* UFER - Uplink FIFO End Register */
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#define FT1000_REG_MAG_UFSR 0x0006 /* UFSR - Uplink FIFO Status Register */
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#define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register (32-bits) */
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#define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register low-word (16-bits) */
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#define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register high-word (16-bits) */
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#define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status Register */
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#define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect Data Register (32-bits) */
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#define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect Data Register low-word (16-bits) */
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#define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data Register high-word (16-bits) */
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#define FT1000_REG_MAG_WATERMARK 0x002c /* WMARK - Watermark Register */
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#define FT1000_REG_MAG_VERSION 0x0030 /* LLC Version */
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/* Reserved Dual Port RAM offsets for Electrabuzz */
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#define FT1000_DPRAM_TX_BASE 0x0002 /* Host to PC Card Messaging Area */
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#define FT1000_DPRAM_RX_BASE 0x0800 /* PC Card to Host Messaging Area */
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#define FT1000_FIFO_LEN 0x07FC /* total length for DSP FIFO tracking */
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#define FT1000_HI_HO 0x07FE /* heartbeat with HI/HO */
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#define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request to reset dsp */
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#define FT1000_DSP_LED 0x0FFA /* dsp led status for PAD device */
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#define FT1000_DSP_CON_STATE 0x0FF8 /* DSP Connection Status Info */
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#define FT1000_DPRAM_FEFE 0x0002 /* location for dsp ready indicator */
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#define FT1000_DSP_TIMER0 0x1FF0 /* Timer Field from Basestation */
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#define FT1000_DSP_TIMER1 0x1FF2 /* Timer Field from Basestation */
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#define FT1000_DSP_TIMER2 0x1FF4 /* Timer Field from Basestation */
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#define FT1000_DSP_TIMER3 0x1FF6 /* Timer Field from Basestation */
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/* Reserved Dual Port RAM offsets for Magnemite */
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#define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card Messaging Area */
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#define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host Messaging Area */
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#define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP FIFO tracking */
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#define FT1000_MAG_FIFO_LEN_INDX 0x1 /* low-word index */
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#define FT1000_MAG_HI_HO 0x1FF /* heartbeat with HI/HO */
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#define FT1000_MAG_HI_HO_INDX 0x0 /* high-word index */
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#define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for PAD device */
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#define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for PAD device */
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#define FT1000_MAG_DSP_CON_STATE 0x3FE /* DSP Connection Status Info */
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#define FT1000_MAG_DSP_CON_STATE_INDX 0x1 /* DSP Connection Status Info */
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#define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready indicator */
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#define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready indicator */
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#define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from Basestation */
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#define FT1000_MAG_DSP_TIMER0_INDX 0x1
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#define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from Basestation */
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#define FT1000_MAG_DSP_TIMER1_INDX 0x0
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#define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from Basestation */
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#define FT1000_MAG_DSP_TIMER2_INDX 0x1
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#define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from Basestation */
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#define FT1000_MAG_DSP_TIMER3_INDX 0x0
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#define FT1000_MAG_TOTAL_LEN 0x200
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#define FT1000_MAG_TOTAL_LEN_INDX 0x1
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#define FT1000_MAG_PH_LEN 0x200
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#define FT1000_MAG_PH_LEN_INDX 0x0
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#define FT1000_MAG_PORT_ID 0x201
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#define FT1000_MAG_PORT_ID_INDX 0x0
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#define HOST_INTF_LE 0x0 /* Host interface little endian mode */
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#define HOST_INTF_BE 0x1 /* Host interface big endian mode */
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/* FT1000 to Host Doorbell assignments */
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#define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP has data for host in DPRAM */
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#define FT1000_DB_DNLD_RX 0x0002 /* Downloader handshake doorbell */
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#define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to reset the ASIC */
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#define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that it will reset the ASIC */
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#define FT1000_DB_COND_RESET 0x0010 /* DSP request for a card reset. */
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/* Host to FT1000 Doorbell assignments */
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#define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host has data for DSP in DPRAM. */
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#define FT1000_DB_DNLD_TX 0x0200 /* Downloader handshake doorbell */
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#define FT1000_ASIC_RESET_DSP 0x0400 /* Responds to FT1000_ASIC_RESET_REQ */
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#define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a heartbeat message for DSP. */
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#define hi 0x6869 /* PC Card heartbeat values */
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#define ho 0x686f /* PC Card heartbeat values */
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/* Magnemite specific defines */
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#define hi_mag 0x6968 /* Byte swap hi to avoid additional system call */
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#define ho_mag 0x6f68 /* Byte swap ho to avoid additional system call */
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/* Bit field definitions for Host Interrupt Status Register */
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/* Indicate the cause of an interrupt. */
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#define ISR_EMPTY 0x00 /* no bits set */
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#define ISR_DOORBELL_ACK 0x01 /* Doorbell acknowledge from DSP */
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#define ISR_DOORBELL_PEND 0x02 /* Doorbell pending from DSP */
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#define ISR_RCV 0x04 /* Packet available in Downlink FIFO */
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#define ISR_WATERMARK 0x08 /* Watermark requirements satisfied */
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/* Bit field definition for Host Interrupt Mask */
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#define ISR_MASK_NONE 0x0000 /* no bits set */
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#define ISR_MASK_DOORBELL_ACK 0x0001 /* Doorbell acknowledge mask */
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#define ISR_MASK_DOORBELL_PEND 0x0002 /* Doorbell pending mask */
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#define ISR_MASK_RCV 0x0004 /* Downlink Packet available mask */
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#define ISR_MASK_WATERMARK 0x0008 /* Watermark interrupt mask */
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#define ISR_MASK_ALL 0xffff /* Mask all interrupts */
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/* Default interrupt mask (Enable Doorbell pending and Packet available interrupts) */
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#define ISR_DEFAULT_MASK 0x7ff9
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/* Bit field definition for Host Control Register */
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#define DSP_RESET_BIT 0x0001 /* Bit field to control dsp reset state */
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/* (0 = out of reset 1 = reset) */
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#define ASIC_RESET_BIT 0x0002 /* Bit field to control ASIC reset state */
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/* (0 = out of reset 1 = reset) */
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#define DSP_UNENCRYPTED 0x0004
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#define DSP_ENCRYPTED 0x0008
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#define EFUSE_MEM_DISABLE 0x0040
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/* Application specific IDs */
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#define DSPID 0x20
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#define HOSTID 0x10
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#define DSPAIRID 0x90
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#define DRIVERID 0x00
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#define NETWORKID 0x20
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/* Size of DPRAM Message */
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#define MAX_CMD_SQSIZE 1780
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#define ENET_MAX_SIZE 1514
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#define ENET_HEADER_SIZE 14
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#define SLOWQ_TYPE 0
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#define FASTQ_TYPE 1
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#define MAX_DSP_SESS_REC 1024
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#define DSP_QID_OFFSET 4
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/* Driver message types */
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#define MEDIA_STATE 0x0010
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#define TIME_UPDATE 0x0020
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#define DSP_PROVISION 0x0030
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#define DSP_INIT_MSG 0x0050
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#define DSP_HIBERNATE 0x0060
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#define DSP_STORE_INFO 0x0070
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#define DSP_GET_INFO 0x0071
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#define GET_DRV_ERR_RPT_MSG 0x0073
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#define RSP_DRV_ERR_RPT_MSG 0x0074
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/* Driver Error Messages for DSP */
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#define DSP_HB_INFO 0x7ef0
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#define DSP_FIFO_INFO 0x7ef1
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#define DSP_CONDRESET_INFO 0x7ef2
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#define DSP_CMDLEN_INFO 0x7ef3
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#define DSP_CMDPHCKSUM_INFO 0x7ef4
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#define DSP_PKTPHCKSUM_INFO 0x7ef5
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#define DSP_PKTLEN_INFO 0x7ef6
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#define DSP_USER_RESET 0x7ef7
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#define FIFO_FLUSH_MAXLIMIT 0x7ef8
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#define FIFO_FLUSH_BADCNT 0x7ef9
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#define FIFO_ZERO_LEN 0x7efa
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/* Pseudo Header structure */
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struct pseudo_hdr {
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unsigned short length; /* length of msg body */
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unsigned char source; /* hardware source id */
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/* Host = 0x10 */
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/* Dsp = 0x20 */
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unsigned char destination; /* hardware destination id (refer to source) */
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unsigned char portdest; /* software destination port id */
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/* Host = 0x00 */
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/* Applicaton Broadcast = 0x10 */
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/* Network Stack = 0x20 */
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/* Dsp OAM = 0x80 */
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/* Dsp Airlink = 0x90 */
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/* Dsp Loader = 0xa0 */
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/* Dsp MIP = 0xb0 */
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unsigned char portsrc; /* software source port id (refer to portdest) */
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unsigned short sh_str_id; /* not used */
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unsigned char control; /* not used */
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unsigned char rsvd1;
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unsigned char seq_num; /* message sequence number */
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unsigned char rsvd2;
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unsigned short qos_class; /* not used */
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unsigned short checksum; /* pseudo header checksum */
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} __packed;
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struct drv_msg {
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struct pseudo_hdr pseudo;
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u16 type;
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u16 length;
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u8 data[0];
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} __packed;
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struct media_msg {
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struct pseudo_hdr pseudo;
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u16 type;
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u16 length;
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u16 state;
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u32 ip_addr;
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u32 net_mask;
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u32 gateway;
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u32 dns_1;
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u32 dns_2;
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} __packed;
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struct dsp_init_msg {
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struct pseudo_hdr pseudo;
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u16 type;
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u16 length;
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u8 DspVer[DSPVERSZ]; /* DSP version number */
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u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */
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u8 Sku[SKUSZ]; /* SKU */
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u8 eui64[EUISZ]; /* EUI64 */
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u8 ProductMode[MODESZ]; /* Product Mode (Market/Production) */
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u8 RfCalVer[CALVERSZ]; /* Rf Calibration version */
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u8 RfCalDate[CALDATESZ]; /* Rf Calibration date */
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} __packed;
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struct prov_record {
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struct list_head list;
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u8 *pprov_data;
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};
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struct ft1000_info {
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void *priv;
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struct net_device_stats stats;
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u16 DrvErrNum;
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u16 AsicID;
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int CardReady;
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int registered;
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int mediastate;
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u8 squeseqnum; /* sequence number on slow queue */
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spinlock_t dpram_lock;
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u16 fifo_cnt;
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u8 DspVer[DSPVERSZ]; /* DSP version number */
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u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */
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u8 Sku[SKUSZ]; /* SKU */
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u8 eui64[EUISZ]; /* EUI64 */
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time_t ConTm; /* Connection Time */
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u8 ProductMode[MODESZ];
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u8 RfCalVer[CALVERSZ];
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u8 RfCalDate[CALDATESZ];
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u16 DSP_TIME[4];
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u16 LedStat;
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u16 ConStat;
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u16 ProgConStat;
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struct list_head prov_list;
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u16 DSPInfoBlklen;
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int (*ft1000_reset)(void *);
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u16 DSPInfoBlk[MAX_DSP_SESS_REC];
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union {
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u16 Rec[MAX_DSP_SESS_REC];
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u32 MagRec[MAX_DSP_SESS_REC/2];
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} DSPSess;
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struct proc_dir_entry *ft1000_proc_dir;
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char netdevname[IFNAMSIZ];
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};
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