8e404fffea
Fold together the NAND driver for Goldfish from Arve with cleanups by Jun Nakajima and a tidy up to 3.7 and checkpatch. This provides a virtual flash driver for the Goldfish Android Virtual Platform, and which is normally used as the root file system when testing emulated devices. Signed-off-by: Mike A. Chan <mikechan@google.com> Signed-off-by: Arve Hjønnevåg <arve@android.com> [Ported to handle x86] Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> Signed-off-by: Jun Nakajima <jun.nakajima@intel.com> Signed-off-by: Bruce Beare <bruce.j.beare@intel.com> [Ported to 3.4] Signed-off-by: Tom Keel <thomas.keel@intel.com> [Ported to 3.7 and tided for checkpatch etc] Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/* drivers/mtd/devices/goldfish_nand_reg.h
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**
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** Copyright (C) 2007 Google, Inc.
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**
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** This software is licensed under the terms of the GNU General Public
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** License version 2, as published by the Free Software Foundation, and
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** may be copied, distributed, and modified under those terms.
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**
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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**
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*/
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#ifndef GOLDFISH_NAND_REG_H
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#define GOLDFISH_NAND_REG_H
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enum nand_cmd {
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NAND_CMD_GET_DEV_NAME, /* Write device name for NAND_DEV to NAND_DATA (vaddr) */
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NAND_CMD_READ,
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NAND_CMD_WRITE,
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NAND_CMD_ERASE,
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NAND_CMD_BLOCK_BAD_GET, /* NAND_RESULT is 1 if block is bad, 0 if it is not */
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NAND_CMD_BLOCK_BAD_SET,
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NAND_CMD_READ_WITH_PARAMS,
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NAND_CMD_WRITE_WITH_PARAMS,
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NAND_CMD_ERASE_WITH_PARAMS
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};
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enum nand_dev_flags {
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NAND_DEV_FLAG_READ_ONLY = 0x00000001,
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NAND_DEV_FLAG_CMD_PARAMS_CAP = 0x00000002,
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};
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#define NAND_VERSION_CURRENT (1)
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enum nand_reg {
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/* Global */
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NAND_VERSION = 0x000,
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NAND_NUM_DEV = 0x004,
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NAND_DEV = 0x008,
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/* Dev info */
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NAND_DEV_FLAGS = 0x010,
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NAND_DEV_NAME_LEN = 0x014,
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NAND_DEV_PAGE_SIZE = 0x018,
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NAND_DEV_EXTRA_SIZE = 0x01c,
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NAND_DEV_ERASE_SIZE = 0x020,
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NAND_DEV_SIZE_LOW = 0x028,
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NAND_DEV_SIZE_HIGH = 0x02c,
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/* Command */
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NAND_RESULT = 0x040,
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NAND_COMMAND = 0x044,
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NAND_DATA = 0x048,
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NAND_TRANSFER_SIZE = 0x04c,
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NAND_ADDR_LOW = 0x050,
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NAND_ADDR_HIGH = 0x054,
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NAND_CMD_PARAMS_ADDR_LOW = 0x058,
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NAND_CMD_PARAMS_ADDR_HIGH = 0x05c,
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};
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struct cmd_params {
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uint32_t dev;
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uint32_t addr_low;
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uint32_t addr_high;
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uint32_t transfer_size;
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uint32_t data;
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uint32_t result;
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};
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#endif
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