![Linus Torvalds](/assets/img/avatar_default.png)
Here's the big tty/serial driver patches for 3.9-rc1. More tty port rework and fixes from Jiri here, as well as lots of individual serial driver updates and fixes. All of these have been in the linux-next tree for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iEYEABECAAYFAlEmZYQACgkQMUfUDdst+ylJDgCg0B0nMevUUdM4hLvxunbbiyXM HUEAoIOedqriNNPvX4Bwy0hjeOEaWx0g =vi6x -----END PGP SIGNATURE----- Merge tag 'tty-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty/serial patches from Greg Kroah-Hartman: "Here's the big tty/serial driver patches for 3.9-rc1. More tty port rework and fixes from Jiri here, as well as lots of individual serial driver updates and fixes. All of these have been in the linux-next tree for a while." * tag 'tty-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (140 commits) tty: mxser: improve error handling in mxser_probe() and mxser_module_init() serial: imx: fix uninitialized variable warning serial: tegra: assume CONFIG_OF TTY: do not update atime/mtime on read/write lguest: select CONFIG_TTY to build properly. ARM defconfigs: add missing inclusions of linux/platform_device.h fb/exynos: include platform_device.h ARM: sa1100/assabet: include platform_device.h directly serial: imx: Fix recursive locking bug pps: Fix build breakage from decoupling pps from tty tty: Remove ancient hardpps() pps: Additional cleanups in uart_handle_dcd_change pps: Move timestamp read into PPS code proper pps: Don't crash the machine when exiting will do pps: Fix a use-after free bug when unregistering a source. pps: Use pps_lookup_dev to reduce ldisc coupling pps: Add pps_lookup_dev() function tty: serial: uartlite: Support uartlite on big and little endian systems tty: serial: uartlite: Fix sparse and checkpatch warnings serial/arc-uart: Miscll DT related updates (Grant's review comments) ... Fix up trivial conflicts, mostly just due to the TTY config option clashing with the EXPERIMENTAL removal.
1047 lines
26 KiB
C
1047 lines
26 KiB
C
/*
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* NXP (Philips) SCC+++(SCN+++) serial driver
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*
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* Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
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*
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* Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/console.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/serial-sccnxp.h>
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#define SCCNXP_NAME "uart-sccnxp"
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#define SCCNXP_MAJOR 204
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#define SCCNXP_MINOR 205
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#define SCCNXP_MR_REG (0x00)
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# define MR0_BAUD_NORMAL (0 << 0)
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# define MR0_BAUD_EXT1 (1 << 0)
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# define MR0_BAUD_EXT2 (5 << 0)
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# define MR0_FIFO (1 << 3)
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# define MR0_TXLVL (1 << 4)
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# define MR1_BITS_5 (0 << 0)
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# define MR1_BITS_6 (1 << 0)
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# define MR1_BITS_7 (2 << 0)
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# define MR1_BITS_8 (3 << 0)
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# define MR1_PAR_EVN (0 << 2)
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# define MR1_PAR_ODD (1 << 2)
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# define MR1_PAR_NO (4 << 2)
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# define MR2_STOP1 (7 << 0)
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# define MR2_STOP2 (0xf << 0)
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#define SCCNXP_SR_REG (0x01)
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#define SCCNXP_CSR_REG SCCNXP_SR_REG
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# define SR_RXRDY (1 << 0)
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# define SR_FULL (1 << 1)
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# define SR_TXRDY (1 << 2)
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# define SR_TXEMT (1 << 3)
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# define SR_OVR (1 << 4)
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# define SR_PE (1 << 5)
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# define SR_FE (1 << 6)
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# define SR_BRK (1 << 7)
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#define SCCNXP_CR_REG (0x02)
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# define CR_RX_ENABLE (1 << 0)
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# define CR_RX_DISABLE (1 << 1)
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# define CR_TX_ENABLE (1 << 2)
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# define CR_TX_DISABLE (1 << 3)
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# define CR_CMD_MRPTR1 (0x01 << 4)
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# define CR_CMD_RX_RESET (0x02 << 4)
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# define CR_CMD_TX_RESET (0x03 << 4)
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# define CR_CMD_STATUS_RESET (0x04 << 4)
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# define CR_CMD_BREAK_RESET (0x05 << 4)
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# define CR_CMD_START_BREAK (0x06 << 4)
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# define CR_CMD_STOP_BREAK (0x07 << 4)
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# define CR_CMD_MRPTR0 (0x0b << 4)
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#define SCCNXP_RHR_REG (0x03)
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#define SCCNXP_THR_REG SCCNXP_RHR_REG
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#define SCCNXP_IPCR_REG (0x04)
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#define SCCNXP_ACR_REG SCCNXP_IPCR_REG
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# define ACR_BAUD0 (0 << 7)
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# define ACR_BAUD1 (1 << 7)
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# define ACR_TIMER_MODE (6 << 4)
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#define SCCNXP_ISR_REG (0x05)
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#define SCCNXP_IMR_REG SCCNXP_ISR_REG
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# define IMR_TXRDY (1 << 0)
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# define IMR_RXRDY (1 << 1)
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# define ISR_TXRDY(x) (1 << ((x * 4) + 0))
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# define ISR_RXRDY(x) (1 << ((x * 4) + 1))
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#define SCCNXP_IPR_REG (0x0d)
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#define SCCNXP_OPCR_REG SCCNXP_IPR_REG
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#define SCCNXP_SOP_REG (0x0e)
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#define SCCNXP_ROP_REG (0x0f)
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/* Route helpers */
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#define MCTRL_MASK(sig) (0xf << (sig))
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#define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
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#define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
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/* Supported chip types */
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enum {
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SCCNXP_TYPE_SC2681 = 2681,
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SCCNXP_TYPE_SC2691 = 2691,
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SCCNXP_TYPE_SC2692 = 2692,
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SCCNXP_TYPE_SC2891 = 2891,
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SCCNXP_TYPE_SC2892 = 2892,
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SCCNXP_TYPE_SC28202 = 28202,
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SCCNXP_TYPE_SC68681 = 68681,
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SCCNXP_TYPE_SC68692 = 68692,
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};
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struct sccnxp_port {
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struct uart_driver uart;
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struct uart_port port[SCCNXP_MAX_UARTS];
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bool opened[SCCNXP_MAX_UARTS];
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const char *name;
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int irq;
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u8 imr;
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u8 addr_mask;
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int freq_std;
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int flags;
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#define SCCNXP_HAVE_IO 0x00000001
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#define SCCNXP_HAVE_MR0 0x00000002
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#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
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struct console console;
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#endif
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spinlock_t lock;
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bool poll;
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struct timer_list timer;
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struct sccnxp_pdata pdata;
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};
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static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift)
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{
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return readb(base + (reg << shift));
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}
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static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v)
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{
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writeb(v, base + (reg << shift));
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}
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static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
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{
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struct sccnxp_port *s = dev_get_drvdata(port->dev);
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return sccnxp_raw_read(port->membase, reg & s->addr_mask,
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port->regshift);
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}
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static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
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{
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struct sccnxp_port *s = dev_get_drvdata(port->dev);
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sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
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}
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static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
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{
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return sccnxp_read(port, (port->line << 3) + reg);
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}
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static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
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{
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sccnxp_write(port, (port->line << 3) + reg, v);
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}
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static int sccnxp_update_best_err(int a, int b, int *besterr)
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{
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int err = abs(a - b);
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if ((*besterr < 0) || (*besterr > err)) {
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*besterr = err;
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return 0;
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}
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return 1;
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}
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static const struct {
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u8 csr;
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u8 acr;
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u8 mr0;
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int baud;
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} baud_std[] = {
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{ 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
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{ 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
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{ 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
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{ 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
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{ 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
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{ 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
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{ 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
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{ 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
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{ 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
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{ 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
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{ 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
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{ 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
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{ 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
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{ 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
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{ 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
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{ 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
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{ 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
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{ 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
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{ 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
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{ 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
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{ 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
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{ 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
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{ 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
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{ 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
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{ 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
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{ 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
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{ 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
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{ 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
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{ 0, 0, 0, 0 }
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};
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static int sccnxp_set_baud(struct uart_port *port, int baud)
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{
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struct sccnxp_port *s = dev_get_drvdata(port->dev);
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int div_std, tmp_baud, bestbaud = baud, besterr = -1;
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u8 i, acr = 0, csr = 0, mr0 = 0;
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/* Find best baud from table */
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for (i = 0; baud_std[i].baud && besterr; i++) {
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if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0))
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continue;
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div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud);
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tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
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if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
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acr = baud_std[i].acr;
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csr = baud_std[i].csr;
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mr0 = baud_std[i].mr0;
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bestbaud = tmp_baud;
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}
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}
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if (s->flags & SCCNXP_HAVE_MR0) {
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/* Enable FIFO, set half level for TX */
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mr0 |= MR0_FIFO | MR0_TXLVL;
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/* Update MR0 */
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sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
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sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
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}
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sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
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sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
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if (baud != bestbaud)
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dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
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baud, bestbaud);
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return bestbaud;
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}
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static void sccnxp_enable_irq(struct uart_port *port, int mask)
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{
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struct sccnxp_port *s = dev_get_drvdata(port->dev);
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s->imr |= mask << (port->line * 4);
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sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
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}
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static void sccnxp_disable_irq(struct uart_port *port, int mask)
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{
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struct sccnxp_port *s = dev_get_drvdata(port->dev);
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s->imr &= ~(mask << (port->line * 4));
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sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
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}
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static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
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{
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u8 bitmask;
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struct sccnxp_port *s = dev_get_drvdata(port->dev);
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if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
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bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
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if (state)
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sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
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else
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sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
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}
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}
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static void sccnxp_handle_rx(struct uart_port *port)
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{
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u8 sr;
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unsigned int ch, flag;
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for (;;) {
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sr = sccnxp_port_read(port, SCCNXP_SR_REG);
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if (!(sr & SR_RXRDY))
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break;
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sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
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ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
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port->icount.rx++;
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flag = TTY_NORMAL;
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if (unlikely(sr)) {
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if (sr & SR_BRK) {
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port->icount.brk++;
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sccnxp_port_write(port, SCCNXP_CR_REG,
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CR_CMD_BREAK_RESET);
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if (uart_handle_break(port))
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continue;
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} else if (sr & SR_PE)
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port->icount.parity++;
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else if (sr & SR_FE)
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port->icount.frame++;
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else if (sr & SR_OVR) {
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port->icount.overrun++;
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sccnxp_port_write(port, SCCNXP_CR_REG,
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CR_CMD_STATUS_RESET);
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}
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sr &= port->read_status_mask;
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if (sr & SR_BRK)
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flag = TTY_BREAK;
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else if (sr & SR_PE)
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flag = TTY_PARITY;
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else if (sr & SR_FE)
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flag = TTY_FRAME;
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else if (sr & SR_OVR)
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flag = TTY_OVERRUN;
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}
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if (uart_handle_sysrq_char(port, ch))
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continue;
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if (sr & port->ignore_status_mask)
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continue;
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uart_insert_char(port, sr, SR_OVR, ch, flag);
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}
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tty_flip_buffer_push(&port->state->port);
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}
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static void sccnxp_handle_tx(struct uart_port *port)
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{
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u8 sr;
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struct circ_buf *xmit = &port->state->xmit;
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struct sccnxp_port *s = dev_get_drvdata(port->dev);
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if (unlikely(port->x_char)) {
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sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
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port->icount.tx++;
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port->x_char = 0;
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return;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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/* Disable TX if FIFO is empty */
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if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
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sccnxp_disable_irq(port, IMR_TXRDY);
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/* Set direction to input */
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if (s->flags & SCCNXP_HAVE_IO)
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sccnxp_set_bit(port, DIR_OP, 0);
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}
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return;
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}
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while (!uart_circ_empty(xmit)) {
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sr = sccnxp_port_read(port, SCCNXP_SR_REG);
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if (!(sr & SR_TXRDY))
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break;
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sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static void sccnxp_handle_events(struct sccnxp_port *s)
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{
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int i;
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u8 isr;
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do {
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isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
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isr &= s->imr;
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if (!isr)
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break;
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for (i = 0; i < s->uart.nr; i++) {
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if (s->opened[i] && (isr & ISR_RXRDY(i)))
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sccnxp_handle_rx(&s->port[i]);
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if (s->opened[i] && (isr & ISR_TXRDY(i)))
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sccnxp_handle_tx(&s->port[i]);
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}
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} while (1);
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}
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static void sccnxp_timer(unsigned long data)
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{
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struct sccnxp_port *s = (struct sccnxp_port *)data;
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unsigned long flags;
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|
|
spin_lock_irqsave(&s->lock, flags);
|
|
sccnxp_handle_events(s);
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
if (!timer_pending(&s->timer))
|
|
mod_timer(&s->timer, jiffies +
|
|
usecs_to_jiffies(s->pdata.poll_time_us));
|
|
}
|
|
|
|
static irqreturn_t sccnxp_ist(int irq, void *dev_id)
|
|
{
|
|
struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
sccnxp_handle_events(s);
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void sccnxp_start_tx(struct uart_port *port)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
|
|
/* Set direction to output */
|
|
if (s->flags & SCCNXP_HAVE_IO)
|
|
sccnxp_set_bit(port, DIR_OP, 1);
|
|
|
|
sccnxp_enable_irq(port, IMR_TXRDY);
|
|
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
}
|
|
|
|
static void sccnxp_stop_tx(struct uart_port *port)
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
static void sccnxp_stop_rx(struct uart_port *port)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
}
|
|
|
|
static unsigned int sccnxp_tx_empty(struct uart_port *port)
|
|
{
|
|
u8 val;
|
|
unsigned long flags;
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
val = sccnxp_port_read(port, SCCNXP_SR_REG);
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
|
|
}
|
|
|
|
static void sccnxp_enable_ms(struct uart_port *port)
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned long flags;
|
|
|
|
if (!(s->flags & SCCNXP_HAVE_IO))
|
|
return;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
|
|
sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
|
|
sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
|
|
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
}
|
|
|
|
static unsigned int sccnxp_get_mctrl(struct uart_port *port)
|
|
{
|
|
u8 bitmask, ipr;
|
|
unsigned long flags;
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
|
|
|
|
if (!(s->flags & SCCNXP_HAVE_IO))
|
|
return mctrl;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
|
|
ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
|
|
|
|
if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
|
|
bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
|
|
DSR_IP);
|
|
mctrl &= ~TIOCM_DSR;
|
|
mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
|
|
}
|
|
if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
|
|
bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
|
|
CTS_IP);
|
|
mctrl &= ~TIOCM_CTS;
|
|
mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
|
|
}
|
|
if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
|
|
bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
|
|
DCD_IP);
|
|
mctrl &= ~TIOCM_CAR;
|
|
mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
|
|
}
|
|
if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
|
|
bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
|
|
RNG_IP);
|
|
mctrl &= ~TIOCM_RNG;
|
|
mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
return mctrl;
|
|
}
|
|
|
|
static void sccnxp_break_ctl(struct uart_port *port, int break_state)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
|
|
CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
}
|
|
|
|
static void sccnxp_set_termios(struct uart_port *port,
|
|
struct ktermios *termios, struct ktermios *old)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned long flags;
|
|
u8 mr1, mr2;
|
|
int baud;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
|
|
/* Mask termios capabilities we don't support */
|
|
termios->c_cflag &= ~CMSPAR;
|
|
|
|
/* Disable RX & TX, reset break condition, status and FIFOs */
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
|
|
CR_RX_DISABLE | CR_TX_DISABLE);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
|
|
|
|
/* Word size */
|
|
switch (termios->c_cflag & CSIZE) {
|
|
case CS5:
|
|
mr1 = MR1_BITS_5;
|
|
break;
|
|
case CS6:
|
|
mr1 = MR1_BITS_6;
|
|
break;
|
|
case CS7:
|
|
mr1 = MR1_BITS_7;
|
|
break;
|
|
case CS8:
|
|
default:
|
|
mr1 = MR1_BITS_8;
|
|
break;
|
|
}
|
|
|
|
/* Parity */
|
|
if (termios->c_cflag & PARENB) {
|
|
if (termios->c_cflag & PARODD)
|
|
mr1 |= MR1_PAR_ODD;
|
|
} else
|
|
mr1 |= MR1_PAR_NO;
|
|
|
|
/* Stop bits */
|
|
mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
|
|
|
|
/* Update desired format */
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
|
|
sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
|
|
sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
|
|
|
|
/* Set read status mask */
|
|
port->read_status_mask = SR_OVR;
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= SR_PE | SR_FE;
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
port->read_status_mask |= SR_BRK;
|
|
|
|
/* Set status ignore mask */
|
|
port->ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNBRK)
|
|
port->ignore_status_mask |= SR_BRK;
|
|
if (!(termios->c_cflag & CREAD))
|
|
port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
|
|
|
|
/* Setup baudrate */
|
|
baud = uart_get_baud_rate(port, termios, old, 50,
|
|
(s->flags & SCCNXP_HAVE_MR0) ?
|
|
230400 : 38400);
|
|
baud = sccnxp_set_baud(port, baud);
|
|
|
|
/* Update timeout according to new baud rate */
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
/* Report actual baudrate back to core */
|
|
if (tty_termios_baud_rate(termios))
|
|
tty_termios_encode_baud_rate(termios, baud, baud);
|
|
|
|
/* Enable RX & TX */
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
|
|
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
}
|
|
|
|
static int sccnxp_startup(struct uart_port *port)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
|
|
if (s->flags & SCCNXP_HAVE_IO) {
|
|
/* Outputs are controlled manually */
|
|
sccnxp_write(port, SCCNXP_OPCR_REG, 0);
|
|
}
|
|
|
|
/* Reset break condition, status and FIFOs */
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
|
|
|
|
/* Enable RX & TX */
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
|
|
|
|
/* Enable RX interrupt */
|
|
sccnxp_enable_irq(port, IMR_RXRDY);
|
|
|
|
s->opened[port->line] = 1;
|
|
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sccnxp_shutdown(struct uart_port *port)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
|
|
s->opened[port->line] = 0;
|
|
|
|
/* Disable interrupts */
|
|
sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
|
|
|
|
/* Disable TX & RX */
|
|
sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
|
|
|
|
/* Leave direction to input */
|
|
if (s->flags & SCCNXP_HAVE_IO)
|
|
sccnxp_set_bit(port, DIR_OP, 0);
|
|
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
}
|
|
|
|
static const char *sccnxp_type(struct uart_port *port)
|
|
{
|
|
struct sccnxp_port *s = dev_get_drvdata(port->dev);
|
|
|
|
return (port->type == PORT_SC26XX) ? s->name : NULL;
|
|
}
|
|
|
|
static void sccnxp_release_port(struct uart_port *port)
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
static int sccnxp_request_port(struct uart_port *port)
|
|
{
|
|
/* Do nothing */
|
|
return 0;
|
|
}
|
|
|
|
static void sccnxp_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE)
|
|
port->type = PORT_SC26XX;
|
|
}
|
|
|
|
static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
|
|
{
|
|
if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
|
|
return 0;
|
|
if (s->irq == port->irq)
|
|
return 0;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct uart_ops sccnxp_ops = {
|
|
.tx_empty = sccnxp_tx_empty,
|
|
.set_mctrl = sccnxp_set_mctrl,
|
|
.get_mctrl = sccnxp_get_mctrl,
|
|
.stop_tx = sccnxp_stop_tx,
|
|
.start_tx = sccnxp_start_tx,
|
|
.stop_rx = sccnxp_stop_rx,
|
|
.enable_ms = sccnxp_enable_ms,
|
|
.break_ctl = sccnxp_break_ctl,
|
|
.startup = sccnxp_startup,
|
|
.shutdown = sccnxp_shutdown,
|
|
.set_termios = sccnxp_set_termios,
|
|
.type = sccnxp_type,
|
|
.release_port = sccnxp_release_port,
|
|
.request_port = sccnxp_request_port,
|
|
.config_port = sccnxp_config_port,
|
|
.verify_port = sccnxp_verify_port,
|
|
};
|
|
|
|
#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
|
|
static void sccnxp_console_putchar(struct uart_port *port, int c)
|
|
{
|
|
int tryes = 100000;
|
|
|
|
while (tryes--) {
|
|
if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
|
|
sccnxp_port_write(port, SCCNXP_THR_REG, c);
|
|
break;
|
|
}
|
|
barrier();
|
|
}
|
|
}
|
|
|
|
static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
|
|
{
|
|
struct sccnxp_port *s = (struct sccnxp_port *)co->data;
|
|
struct uart_port *port = &s->port[co->index];
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
uart_console_write(port, c, n, sccnxp_console_putchar);
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
}
|
|
|
|
static int sccnxp_console_setup(struct console *co, char *options)
|
|
{
|
|
struct sccnxp_port *s = (struct sccnxp_port *)co->data;
|
|
struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
|
|
int baud = 9600, bits = 8, parity = 'n', flow = 'n';
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
#endif
|
|
|
|
static int sccnxp_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
int chiptype = pdev->id_entry->driver_data;
|
|
struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
|
|
int i, ret, fifosize, freq_min, freq_max;
|
|
struct sccnxp_port *s;
|
|
void __iomem *membase;
|
|
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "Missing memory resource data\n");
|
|
return -EADDRNOTAVAIL;
|
|
}
|
|
|
|
dev_set_name(&pdev->dev, SCCNXP_NAME);
|
|
|
|
s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
|
|
if (!s) {
|
|
dev_err(&pdev->dev, "Error allocating port structure\n");
|
|
return -ENOMEM;
|
|
}
|
|
platform_set_drvdata(pdev, s);
|
|
|
|
spin_lock_init(&s->lock);
|
|
|
|
/* Individual chip settings */
|
|
switch (chiptype) {
|
|
case SCCNXP_TYPE_SC2681:
|
|
s->name = "SC2681";
|
|
s->uart.nr = 2;
|
|
s->freq_std = 3686400;
|
|
s->addr_mask = 0x0f;
|
|
s->flags = SCCNXP_HAVE_IO;
|
|
fifosize = 3;
|
|
freq_min = 1000000;
|
|
freq_max = 4000000;
|
|
break;
|
|
case SCCNXP_TYPE_SC2691:
|
|
s->name = "SC2691";
|
|
s->uart.nr = 1;
|
|
s->freq_std = 3686400;
|
|
s->addr_mask = 0x07;
|
|
s->flags = 0;
|
|
fifosize = 3;
|
|
freq_min = 1000000;
|
|
freq_max = 4000000;
|
|
break;
|
|
case SCCNXP_TYPE_SC2692:
|
|
s->name = "SC2692";
|
|
s->uart.nr = 2;
|
|
s->freq_std = 3686400;
|
|
s->addr_mask = 0x0f;
|
|
s->flags = SCCNXP_HAVE_IO;
|
|
fifosize = 3;
|
|
freq_min = 1000000;
|
|
freq_max = 4000000;
|
|
break;
|
|
case SCCNXP_TYPE_SC2891:
|
|
s->name = "SC2891";
|
|
s->uart.nr = 1;
|
|
s->freq_std = 3686400;
|
|
s->addr_mask = 0x0f;
|
|
s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
|
|
fifosize = 16;
|
|
freq_min = 100000;
|
|
freq_max = 8000000;
|
|
break;
|
|
case SCCNXP_TYPE_SC2892:
|
|
s->name = "SC2892";
|
|
s->uart.nr = 2;
|
|
s->freq_std = 3686400;
|
|
s->addr_mask = 0x0f;
|
|
s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
|
|
fifosize = 16;
|
|
freq_min = 100000;
|
|
freq_max = 8000000;
|
|
break;
|
|
case SCCNXP_TYPE_SC28202:
|
|
s->name = "SC28202";
|
|
s->uart.nr = 2;
|
|
s->freq_std = 14745600;
|
|
s->addr_mask = 0x7f;
|
|
s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
|
|
fifosize = 256;
|
|
freq_min = 1000000;
|
|
freq_max = 50000000;
|
|
break;
|
|
case SCCNXP_TYPE_SC68681:
|
|
s->name = "SC68681";
|
|
s->uart.nr = 2;
|
|
s->freq_std = 3686400;
|
|
s->addr_mask = 0x0f;
|
|
s->flags = SCCNXP_HAVE_IO;
|
|
fifosize = 3;
|
|
freq_min = 1000000;
|
|
freq_max = 4000000;
|
|
break;
|
|
case SCCNXP_TYPE_SC68692:
|
|
s->name = "SC68692";
|
|
s->uart.nr = 2;
|
|
s->freq_std = 3686400;
|
|
s->addr_mask = 0x0f;
|
|
s->flags = SCCNXP_HAVE_IO;
|
|
fifosize = 3;
|
|
freq_min = 1000000;
|
|
freq_max = 4000000;
|
|
break;
|
|
default:
|
|
dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
|
|
ret = -ENOTSUPP;
|
|
goto err_out;
|
|
}
|
|
|
|
if (!pdata) {
|
|
dev_warn(&pdev->dev,
|
|
"No platform data supplied, using defaults\n");
|
|
s->pdata.frequency = s->freq_std;
|
|
} else
|
|
memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
|
|
|
|
if (s->pdata.poll_time_us) {
|
|
dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
|
|
s->pdata.poll_time_us);
|
|
s->poll = 1;
|
|
}
|
|
|
|
if (!s->poll) {
|
|
s->irq = platform_get_irq(pdev, 0);
|
|
if (s->irq < 0) {
|
|
dev_err(&pdev->dev, "Missing irq resource data\n");
|
|
ret = -ENXIO;
|
|
goto err_out;
|
|
}
|
|
}
|
|
|
|
/* Check input frequency */
|
|
if ((s->pdata.frequency < freq_min) ||
|
|
(s->pdata.frequency > freq_max)) {
|
|
dev_err(&pdev->dev, "Frequency out of bounds\n");
|
|
ret = -EINVAL;
|
|
goto err_out;
|
|
}
|
|
|
|
membase = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(membase)) {
|
|
ret = PTR_ERR(membase);
|
|
goto err_out;
|
|
}
|
|
|
|
s->uart.owner = THIS_MODULE;
|
|
s->uart.dev_name = "ttySC";
|
|
s->uart.major = SCCNXP_MAJOR;
|
|
s->uart.minor = SCCNXP_MINOR;
|
|
#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
|
|
s->uart.cons = &s->console;
|
|
s->uart.cons->device = uart_console_device;
|
|
s->uart.cons->write = sccnxp_console_write;
|
|
s->uart.cons->setup = sccnxp_console_setup;
|
|
s->uart.cons->flags = CON_PRINTBUFFER;
|
|
s->uart.cons->index = -1;
|
|
s->uart.cons->data = s;
|
|
strcpy(s->uart.cons->name, "ttySC");
|
|
#endif
|
|
ret = uart_register_driver(&s->uart);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Registering UART driver failed\n");
|
|
goto err_out;
|
|
}
|
|
|
|
for (i = 0; i < s->uart.nr; i++) {
|
|
s->port[i].line = i;
|
|
s->port[i].dev = &pdev->dev;
|
|
s->port[i].irq = s->irq;
|
|
s->port[i].type = PORT_SC26XX;
|
|
s->port[i].fifosize = fifosize;
|
|
s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
|
|
s->port[i].iotype = UPIO_MEM;
|
|
s->port[i].mapbase = res->start;
|
|
s->port[i].membase = membase;
|
|
s->port[i].regshift = s->pdata.reg_shift;
|
|
s->port[i].uartclk = s->pdata.frequency;
|
|
s->port[i].ops = &sccnxp_ops;
|
|
uart_add_one_port(&s->uart, &s->port[i]);
|
|
/* Set direction to input */
|
|
if (s->flags & SCCNXP_HAVE_IO)
|
|
sccnxp_set_bit(&s->port[i], DIR_OP, 0);
|
|
}
|
|
|
|
/* Disable interrupts */
|
|
s->imr = 0;
|
|
sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
|
|
|
|
/* Board specific configure */
|
|
if (s->pdata.init)
|
|
s->pdata.init();
|
|
|
|
if (!s->poll) {
|
|
ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
|
|
sccnxp_ist,
|
|
IRQF_TRIGGER_FALLING |
|
|
IRQF_ONESHOT,
|
|
dev_name(&pdev->dev), s);
|
|
if (!ret)
|
|
return 0;
|
|
|
|
dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
|
|
} else {
|
|
init_timer(&s->timer);
|
|
setup_timer(&s->timer, sccnxp_timer, (unsigned long)s);
|
|
mod_timer(&s->timer, jiffies +
|
|
usecs_to_jiffies(s->pdata.poll_time_us));
|
|
return 0;
|
|
}
|
|
|
|
err_out:
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sccnxp_remove(struct platform_device *pdev)
|
|
{
|
|
int i;
|
|
struct sccnxp_port *s = platform_get_drvdata(pdev);
|
|
|
|
if (!s->poll)
|
|
devm_free_irq(&pdev->dev, s->irq, s);
|
|
else
|
|
del_timer_sync(&s->timer);
|
|
|
|
for (i = 0; i < s->uart.nr; i++)
|
|
uart_remove_one_port(&s->uart, &s->port[i]);
|
|
|
|
uart_unregister_driver(&s->uart);
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
if (s->pdata.exit)
|
|
s->pdata.exit();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id sccnxp_id_table[] = {
|
|
{ "sc2681", SCCNXP_TYPE_SC2681 },
|
|
{ "sc2691", SCCNXP_TYPE_SC2691 },
|
|
{ "sc2692", SCCNXP_TYPE_SC2692 },
|
|
{ "sc2891", SCCNXP_TYPE_SC2891 },
|
|
{ "sc2892", SCCNXP_TYPE_SC2892 },
|
|
{ "sc28202", SCCNXP_TYPE_SC28202 },
|
|
{ "sc68681", SCCNXP_TYPE_SC68681 },
|
|
{ "sc68692", SCCNXP_TYPE_SC68692 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
|
|
|
|
static struct platform_driver sccnxp_uart_driver = {
|
|
.driver = {
|
|
.name = SCCNXP_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = sccnxp_probe,
|
|
.remove = sccnxp_remove,
|
|
.id_table = sccnxp_id_table,
|
|
};
|
|
module_platform_driver(sccnxp_uart_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
|
|
MODULE_DESCRIPTION("SCCNXP serial driver");
|