015d859193
Devices that utilize the OCP registers and/or PRCM registers and register bit fields should be modeled using hwmod. Since eQEP, ePWM and eCAP don't fall under this category, remove their hwmod entries. Instead these clocks simply use the clock that is passed through by its parent PWMSS. Therefore, PWMSS handles the clock for itself and its subdevices. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
621 lines
15 KiB
C
621 lines
15 KiB
C
/*
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* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
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*
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* Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is automatically generated from the AM33XX hardware databases.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/i2c-omap.h>
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#include "omap_hwmod.h"
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#include <linux/platform_data/gpio-omap.h>
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#include <linux/platform_data/spi-omap2-mcspi.h>
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#include "omap_hwmod_common_data.h"
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#include "control.h"
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#include "cm33xx.h"
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#include "prm33xx.h"
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#include "prm-regbits-33xx.h"
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#include "i2c.h"
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#include "wd_timer.h"
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#include "omap_hwmod_33xx_43xx_common_data.h"
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/*
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* IP blocks
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*/
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/* emif */
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static struct omap_hwmod am33xx_emif_hwmod = {
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.name = "emif",
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.class = &am33xx_emif_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_ddr_m2_div2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* l4_hs */
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static struct omap_hwmod am33xx_l4_hs_hwmod = {
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.name = "l4_hs",
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.class = &am33xx_l4_hwmod_class,
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.clkdm_name = "l4hs_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l4hs_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
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{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
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};
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/* wkup_m3 */
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static struct omap_hwmod am33xx_wkup_m3_hwmod = {
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.name = "wkup_m3",
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.class = &am33xx_wkup_m3_hwmod_class,
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.clkdm_name = "l4_wkup_aon_clkdm",
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/* Keep hardreset asserted */
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.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
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.main_clk = "dpll_core_m4_div2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
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.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
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.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.rst_lines = am33xx_wkup_m3_resets,
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.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
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};
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/*
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* 'adc/tsc' class
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* TouchScreen Controller (Anolog-To-Digital Converter)
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*/
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static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
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.rev_offs = 0x00,
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.sysc_offs = 0x10,
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.sysc_flags = SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
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.name = "adc_tsc",
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.sysc = &am33xx_adc_tsc_sysc,
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};
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static struct omap_hwmod am33xx_adc_tsc_hwmod = {
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.name = "adc_tsc",
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.class = &am33xx_adc_tsc_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.main_clk = "adc_tsc_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* Modules omap_hwmod structures
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*
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* The following IPs are excluded for the moment because:
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* - They do not need an explicit SW control using omap_hwmod API.
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* - They still need to be validated with the driver
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* properly adapted to omap_hwmod / omap_device
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*
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* - cEFUSE (doesn't fall under any ocp_if)
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* - clkdiv32k
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* - ocp watch point
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*/
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#if 0
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/*
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* 'cefuse' class
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*/
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static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
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.name = "cefuse",
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};
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static struct omap_hwmod am33xx_cefuse_hwmod = {
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.name = "cefuse",
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.class = &am33xx_cefuse_hwmod_class,
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.clkdm_name = "l4_cefuse_clkdm",
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.main_clk = "cefuse_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'clkdiv32k' class
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*/
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static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
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.name = "clkdiv32k",
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};
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static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
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.name = "clkdiv32k",
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.class = &am33xx_clkdiv32k_hwmod_class,
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.clkdm_name = "clk_24mhz_clkdm",
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.main_clk = "clkdiv32k_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* ocpwp */
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static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
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.name = "ocpwp",
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};
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static struct omap_hwmod am33xx_ocpwp_hwmod = {
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.name = "ocpwp",
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.class = &am33xx_ocpwp_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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#endif
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/*
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* 'debugss' class
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* debug sub system
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*/
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static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
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{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
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{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
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};
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static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
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.name = "debugss",
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};
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static struct omap_hwmod am33xx_debugss_hwmod = {
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.name = "debugss",
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.class = &am33xx_debugss_hwmod_class,
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.clkdm_name = "l3_aon_clkdm",
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.main_clk = "trace_clk_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = debugss_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
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};
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static struct omap_hwmod am33xx_control_hwmod = {
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.name = "control",
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.class = &am33xx_control_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_core_m4_div2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* gpio0 */
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static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
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{ .role = "dbclk", .clk = "gpio0_dbclk" },
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};
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static struct omap_hwmod am33xx_gpio0_hwmod = {
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.name = "gpio1",
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.class = &am33xx_gpio_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "dpll_core_m4_div2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio0_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
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.dev_attr = &gpio_dev_attr,
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};
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/* lcdc */
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static struct omap_hwmod_class_sysconfig lcdc_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x54,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
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.name = "lcdc",
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.sysc = &lcdc_sysc,
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};
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static struct omap_hwmod am33xx_lcdc_hwmod = {
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.name = "lcdc",
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.class = &am33xx_lcdc_hwmod_class,
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.clkdm_name = "lcdc_clkdm",
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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.main_clk = "lcd_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'usb_otg' class
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* high-speed on-the-go universal serial bus (usb_otg) controller
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*/
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static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x10,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class am33xx_usbotg_class = {
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.name = "usbotg",
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.sysc = &am33xx_usbhsotg_sysc,
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};
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static struct omap_hwmod am33xx_usbss_hwmod = {
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.name = "usb_otg_hs",
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.class = &am33xx_usbotg_class,
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.clkdm_name = "l3s_clkdm",
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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.main_clk = "usbotg_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* Interfaces
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*/
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static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
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{
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.pa_start = 0x4c000000,
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.pa_end = 0x4c000fff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l3 main -> emif */
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static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am33xx_emif_hwmod,
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.clk = "dpll_core_m4_ck",
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.addr = am33xx_emif_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3 main -> l4 hs */
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static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am33xx_l4_hs_hwmod,
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.clk = "l3s_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* wkup m3 -> l4 wkup */
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static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
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.master = &am33xx_wkup_m3_hwmod,
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.slave = &am33xx_l4_wkup_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4 wkup -> wkup m3 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_wkup_m3_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4 hs -> pru-icss */
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static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
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.master = &am33xx_l4_hs_hwmod,
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.slave = &am33xx_pruss_hwmod,
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.clk = "dpll_core_m4_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main -> debugss */
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static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
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{
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.pa_start = 0x4b000000,
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.pa_end = 0x4b000000 + SZ_16M - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am33xx_debugss_hwmod,
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.clk = "dpll_core_m4_ck",
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.addr = am33xx_debugss_addrs,
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.user = OCP_USER_MPU,
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};
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/* l4 wkup -> smartreflex0 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_smartreflex0_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU,
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};
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/* l4 wkup -> smartreflex1 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_smartreflex1_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU,
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};
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/* l4 wkup -> control */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_control_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU,
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};
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/* L4 WKUP -> I2C1 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_i2c1_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU,
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};
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/* L4 WKUP -> GPIO1 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_gpio0_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 WKUP -> ADC_TSC */
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static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
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{
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.pa_start = 0x44E0D000,
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.pa_end = 0x44E0D000 + SZ_8K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_adc_tsc_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.addr = am33xx_adc_tsc_addrs,
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.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
|
|
.master = &am33xx_l4_hs_hwmod,
|
|
.slave = &am33xx_cpgmac0_hwmod,
|
|
.clk = "cpsw_125mhz_gclk",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
|
|
{
|
|
.pa_start = 0x4830E000,
|
|
.pa_end = 0x4830E000 + SZ_8K - 1,
|
|
.flags = ADDR_TYPE_RT,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
|
|
.master = &am33xx_l3_main_hwmod,
|
|
.slave = &am33xx_lcdc_hwmod,
|
|
.clk = "dpll_core_m4_ck",
|
|
.addr = am33xx_lcdc_addr_space,
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l4 wkup -> timer1 */
|
|
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_timer1_hwmod,
|
|
.clk = "dpll_core_m4_div2_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l4 wkup -> uart1 */
|
|
static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_uart1_hwmod,
|
|
.clk = "dpll_core_m4_div2_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l4 wkup -> wd_timer1 */
|
|
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
|
|
.master = &am33xx_l4_wkup_hwmod,
|
|
.slave = &am33xx_wd_timer1_hwmod,
|
|
.clk = "dpll_core_m4_div2_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* usbss */
|
|
/* l3 s -> USBSS interface */
|
|
static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
|
|
.master = &am33xx_l3_s_hwmod,
|
|
.slave = &am33xx_usbss_hwmod,
|
|
.clk = "l3s_gclk",
|
|
.user = OCP_USER_MPU,
|
|
.flags = OCPIF_SWSUP_IDLE,
|
|
};
|
|
|
|
/* rng */
|
|
static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
|
|
.rev_offs = 0x1fe0,
|
|
.sysc_offs = 0x1fe4,
|
|
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = SIDLE_FORCE | SIDLE_NO,
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_rng_hwmod_class = {
|
|
.name = "rng",
|
|
.sysc = &am33xx_rng_sysc,
|
|
};
|
|
|
|
static struct omap_hwmod am33xx_rng_hwmod = {
|
|
.name = "rng",
|
|
.class = &am33xx_rng_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE,
|
|
.main_clk = "rng_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
|
|
.master = &am33xx_l4_ls_hwmod,
|
|
.slave = &am33xx_rng_hwmod,
|
|
.clk = "rng_fck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
|
|
&am33xx_l3_main__emif,
|
|
&am33xx_mpu__l3_main,
|
|
&am33xx_mpu__prcm,
|
|
&am33xx_l3_s__l4_ls,
|
|
&am33xx_l3_s__l4_wkup,
|
|
&am33xx_l3_main__l4_hs,
|
|
&am33xx_l3_main__l3_s,
|
|
&am33xx_l3_main__l3_instr,
|
|
&am33xx_l3_main__gfx,
|
|
&am33xx_l3_s__l3_main,
|
|
&am33xx_pruss__l3_main,
|
|
&am33xx_wkup_m3__l4_wkup,
|
|
&am33xx_gfx__l3_main,
|
|
&am33xx_l3_main__debugss,
|
|
&am33xx_l4_wkup__wkup_m3,
|
|
&am33xx_l4_wkup__control,
|
|
&am33xx_l4_wkup__smartreflex0,
|
|
&am33xx_l4_wkup__smartreflex1,
|
|
&am33xx_l4_wkup__uart1,
|
|
&am33xx_l4_wkup__timer1,
|
|
&am33xx_l4_wkup__rtc,
|
|
&am33xx_l4_wkup__i2c1,
|
|
&am33xx_l4_wkup__gpio0,
|
|
&am33xx_l4_wkup__adc_tsc,
|
|
&am33xx_l4_wkup__wd_timer1,
|
|
&am33xx_l4_hs__pruss,
|
|
&am33xx_l4_per__dcan0,
|
|
&am33xx_l4_per__dcan1,
|
|
&am33xx_l4_per__gpio1,
|
|
&am33xx_l4_per__gpio2,
|
|
&am33xx_l4_per__gpio3,
|
|
&am33xx_l4_per__i2c2,
|
|
&am33xx_l4_per__i2c3,
|
|
&am33xx_l4_per__mailbox,
|
|
&am33xx_l4_ls__mcasp0,
|
|
&am33xx_l4_ls__mcasp1,
|
|
&am33xx_l4_ls__mmc0,
|
|
&am33xx_l4_ls__mmc1,
|
|
&am33xx_l3_s__mmc2,
|
|
&am33xx_l4_ls__timer2,
|
|
&am33xx_l4_ls__timer3,
|
|
&am33xx_l4_ls__timer4,
|
|
&am33xx_l4_ls__timer5,
|
|
&am33xx_l4_ls__timer6,
|
|
&am33xx_l4_ls__timer7,
|
|
&am33xx_l3_main__tpcc,
|
|
&am33xx_l4_ls__uart2,
|
|
&am33xx_l4_ls__uart3,
|
|
&am33xx_l4_ls__uart4,
|
|
&am33xx_l4_ls__uart5,
|
|
&am33xx_l4_ls__uart6,
|
|
&am33xx_l4_ls__spinlock,
|
|
&am33xx_l4_ls__elm,
|
|
&am33xx_l4_ls__epwmss0,
|
|
&am33xx_l4_ls__epwmss1,
|
|
&am33xx_l4_ls__epwmss2,
|
|
&am33xx_l3_s__gpmc,
|
|
&am33xx_l3_main__lcdc,
|
|
&am33xx_l4_ls__mcspi0,
|
|
&am33xx_l4_ls__mcspi1,
|
|
&am33xx_l3_main__tptc0,
|
|
&am33xx_l3_main__tptc1,
|
|
&am33xx_l3_main__tptc2,
|
|
&am33xx_l3_main__ocmc,
|
|
&am33xx_l3_s__usbss,
|
|
&am33xx_l4_hs__cpgmac0,
|
|
&am33xx_cpgmac0__mdio,
|
|
&am33xx_l3_main__sha0,
|
|
&am33xx_l3_main__aes0,
|
|
&am33xx_l4_per__rng,
|
|
NULL,
|
|
};
|
|
|
|
int __init am33xx_hwmod_init(void)
|
|
{
|
|
omap_hwmod_am33xx_reg();
|
|
omap_hwmod_init();
|
|
return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
|
|
}
|