9896c7b57e
We get support for three new 32-bit SoC platforms this time. The amount of changes in arch/arm for any of them is miniscule, as all the interesting code is in device driver subsystems (irqchip, clk, pinctrl, ...) these days. I'm listing them here, as the addition of the Kconfig statement is the main relevant milestone for a new platform. In each case, some drivers are are shared with existing platforms, while other drivers are added for v4.7 as well, or come in a later release. - The Aspeed platform is probably the most interesting one, this is what most whitebox servers use as their baseboard management controller. We get support for the very common ast2400 and ast2500 SoCs. The OpenBMC project focuses on this chip, and the LWN article about their ELC 2016 presentation at https://lwn.net/Articles/683320/ triggered the submission, but the code comes from IBM's OpenPOWER team rather than the team at Facebook. There are still a lot more drivers that need to get added over time, and I hope both teams can work together on that. - OXNAS is an old platform for Network Attached Storage devices from Oxford Semiconductor. There are models with ARM10 (!) and ARM11MPCore cores, but for now, we only support the original ARM9 based versions. The product lineup was subsequently part of PLX, Avago and now the new Broadcom Ltd. https://wiki.openwrt.org/doc/hardware/soc/soc.oxnas has some more information. - V2M-MPS2 is a prototyping platform from ARM for their Cortex-M cores and is related to the existing Realview / Versatile Express lineup, but without MMU. We now support various NOMMU platforms, so adding a new one is fairly straightforward. http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/ has detailed information about the platform. Other noteworthy updates: - Work on LPC32xx has resumed, and Vladimir Zapolskiy and Sylvain Lemieux are now maintaining the platform. This is an older ARM9 based platform from NXP (not Freescale), but it remains in use in embedded markets. - Kevin Hilman is now co-maintaining the Amlogic Meson platform for both 32-bit and 64-bit ARM, and started contributing some patches. - As is often the case, work on the OMAP platforms makes up the bulk of the actual SoC code changes in arch/arm, but there isn't a lot of that either. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAVzuXX2CrR//JCVInAQLTghAA0f+2V2wC6HVBfDhT1YmhbAkPF1KzgLbB h30fN6BtIe9mE3kR69uWgwPSzn4hTKEQXoC9m6S+XClTn6MKPrbCEYDZl4ZwIER8 XDamxJV+6oTG+GKtKpHFkC4WPJkLthEuD34gr2xU8DFrU+y2Y5QNXi5wvSsBp8WS 6C/70HQEy35uSyOjbjVlPi0/UKoelVw9dCO7HZBOb9lTd88hC4Gx90KFwpq6Ievf L20VNgOESC2y6kRbuLNbhQVsbT2Ijyz9NccVM5owFEbHkXDxJ0vQVzrNM999DVjb CC2v0NZMLPNJQn2RvC172QBOsOERxIRkZdJHcifydl7i2QNpr8+/YSnS7OSx3dA/ 3ZmTLejaiGUXdTGEI9dHy77s+adwTzGsH+INKotQG8qwUXzCLuUWN3GGK+Qof5Rk jbsGAoZ7GQz1/7NdEOcGW6pxD4mllk3McKMzNlMmddRDUPhSUg3WXu0c1AWGzfA1 ulk6fQDaTUjvs7nokuozhguKz8OKrT6S7x/iES5tPbXLhuDqfnUdYiQ+7m2beRb5 L9S9KK95HXnKJAI9WLOELj1vCrfbCGjlwz8YVSrwPtwwzP/wbB1Ni6tmwLrxHbLk SGyJEMnPs3mARIPDwDysyOs+3OUSx04uYW6YTSh8XyKNIxTCflRxr/iM5YyYEMvt lXMrp1sh4hc= =5oFu -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "We get support for three new 32-bit SoC platforms this time. The amount of changes in arch/arm for any of them is miniscule, as all the interesting code is in device driver subsystems (irqchip, clk, pinctrl, ...) these days. I'm listing them here, as the addition of the Kconfig statement is the main relevant milestone for a new platform. In each case, some drivers are are shared with existing platforms, while other drivers are added for v4.7 as well, or come in a later release. - The Aspeed platform is probably the most interesting one, this is what most whitebox servers use as their baseboard management controller. We get support for the very common ast2400 and ast2500 SoCs. The OpenBMC project focuses on this chip, and the LWN article about their ELC 2016 presentation at https://lwn.net/Articles/683320/ triggered the submission, but the code comes from IBM's OpenPOWER team rather than the team at Facebook. There are still a lot more drivers that need to get added over time, and I hope both teams can work together on that. - OXNAS is an old platform for Network Attached Storage devices from Oxford Semiconductor. There are models with ARM10 (!) and ARM11MPCore cores, but for now, we only support the original ARM9 based versions. The product lineup was subsequently part of PLX, Avago and now the new Broadcom Ltd. https://wiki.openwrt.org/doc/hardware/soc/soc.oxnas has some more information. - V2M-MPS2 is a prototyping platform from ARM for their Cortex-M cores and is related to the existing Realview / Versatile Express lineup, but without MMU. We now support various NOMMU platforms, so adding a new one is fairly straightforward. http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/ has detailed information about the platform. Other noteworthy updates: - Work on LPC32xx has resumed, and Vladimir Zapolskiy and Sylvain Lemieux are now maintaining the platform. This is an older ARM9 based platform from NXP (not Freescale), but it remains in use in embedded markets. - Kevin Hilman is now co-maintaining the Amlogic Meson platform for both 32-bit and 64-bit ARM, and started contributing some patches. - As is often the case, work on the OMAP platforms makes up the bulk of the actual SoC code changes in arch/arm, but there isn't a lot of that either" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) MAINTAINERS: ARM/Amlogic: add co-maintainer, misc. updates MAINTAINERS: add ARM/NXP LPC32XX SoC specific drivers to the section MAINTAINERS: add new maintainers of NXP LPC32xx SoC MAINTAINERS: move ARM/NXP LPC32xx record to ARM section arm: Add Aspeed machine ARM: lpc32xx: remove duplicate const on lpc32xx_auxdata_lookup ARM: lpc32xx: remove leftovers of legacy clock source and provider drivers ARM: lpc32xx: remove reboot header file ARM: dove: Remove CLK_IS_ROOT ARM: orion5x: Remove CLK_IS_ROOT ARM: mv78xx0: Remove CLK_IS_ROOT ARM: davinci: da850: use clk->set_parent for async3 ARM: davinci: Move clock init after ioremap. MAINTAINERS: Update ARM Versatile Express platform entry ARM: vexpress/mps2: introduce MPS2 platform MAINTAINERS: add maintainer entry for ARM/OXNAS platform ARM: Add new mach-oxnas irqchip: versatile-fpga: add new compatible for OX810SE SoC ARM: uniphier: correct the call order of of_node_put() MAINTAINERS: fix stale TI DaVinci entries ...
498 lines
14 KiB
C
498 lines
14 KiB
C
/*
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* OMAP cpu type detection
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*
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* Copyright (C) 2004, 2008 Nokia Corporation
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*
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* Copyright (C) 2009-11 Texas Instruments.
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*
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* Written by Tony Lindgren <tony.lindgren@nokia.com>
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*
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* Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
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* Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "omap24xx.h"
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#include "omap34xx.h"
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#include "omap44xx.h"
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#include "ti81xx.h"
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#include "am33xx.h"
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#include "omap54xx.h"
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#include <linux/of.h>
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/*
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* OMAP2+ is always defined as ARCH_MULTIPLATFORM in Kconfig
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*/
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#undef MULTI_OMAP2
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#define MULTI_OMAP2
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/*
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* Omap device type i.e. EMU/HS/TST/GP/BAD
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*/
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#define OMAP2_DEVICE_TYPE_TEST 0
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#define OMAP2_DEVICE_TYPE_EMU 1
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#define OMAP2_DEVICE_TYPE_SEC 2
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#define OMAP2_DEVICE_TYPE_GP 3
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#define OMAP2_DEVICE_TYPE_BAD 4
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int omap_type(void);
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/*
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* omap_rev bits:
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* SoC id bits (0730, 1510, 1710, 2422...) [31:16]
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* SoC revision (See _REV_ defined in cpu.h) [15:08]
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* SoC class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
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*/
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unsigned int omap_rev(void);
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static inline int soc_is_omap(void)
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{
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return omap_rev() != 0;
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}
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/*
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* Get the SoC revision for OMAP devices
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*/
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#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
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/*
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* Macros to group OMAP into cpu classes.
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* These can be used in most places.
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* soc_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
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* soc_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
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* soc_is_omap243x(): True for OMAP2430
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* soc_is_omap343x(): True for OMAP3430
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* soc_is_omap443x(): True for OMAP4430
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* soc_is_omap446x(): True for OMAP4460
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* soc_is_omap447x(): True for OMAP4470
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* soc_is_omap543x(): True for OMAP5430, OMAP5432
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*/
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#define GET_OMAP_CLASS (omap_rev() & 0xff)
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#define IS_OMAP_CLASS(class, id) \
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static inline int is_omap ##class (void) \
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{ \
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return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
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}
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#define GET_AM_CLASS ((omap_rev() >> 24) & 0xff)
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#define IS_AM_CLASS(class, id) \
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static inline int is_am ##class (void) \
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{ \
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return (GET_AM_CLASS == (id)) ? 1 : 0; \
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}
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#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff)
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#define IS_TI_CLASS(class, id) \
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static inline int is_ti ##class (void) \
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{ \
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return (GET_TI_CLASS == (id)) ? 1 : 0; \
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}
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#define GET_DRA_CLASS ((omap_rev() >> 24) & 0xff)
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#define IS_DRA_CLASS(class, id) \
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static inline int is_dra ##class (void) \
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{ \
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return (GET_DRA_CLASS == (id)) ? 1 : 0; \
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}
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#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
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#define IS_OMAP_SUBCLASS(subclass, id) \
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static inline int is_omap ##subclass (void) \
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{ \
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return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
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}
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#define IS_TI_SUBCLASS(subclass, id) \
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static inline int is_ti ##subclass (void) \
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{ \
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return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
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}
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#define IS_AM_SUBCLASS(subclass, id) \
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static inline int is_am ##subclass (void) \
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{ \
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return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
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}
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#define IS_DRA_SUBCLASS(subclass, id) \
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static inline int is_dra ##subclass (void) \
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{ \
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return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
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}
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IS_OMAP_CLASS(24xx, 0x24)
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IS_OMAP_CLASS(34xx, 0x34)
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IS_OMAP_CLASS(44xx, 0x44)
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IS_AM_CLASS(35xx, 0x35)
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IS_OMAP_CLASS(54xx, 0x54)
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IS_AM_CLASS(33xx, 0x33)
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IS_AM_CLASS(43xx, 0x43)
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IS_TI_CLASS(81xx, 0x81)
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IS_DRA_CLASS(7xx, 0x7)
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IS_OMAP_SUBCLASS(242x, 0x242)
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IS_OMAP_SUBCLASS(243x, 0x243)
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IS_OMAP_SUBCLASS(343x, 0x343)
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IS_OMAP_SUBCLASS(363x, 0x363)
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IS_OMAP_SUBCLASS(443x, 0x443)
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IS_OMAP_SUBCLASS(446x, 0x446)
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IS_OMAP_SUBCLASS(447x, 0x447)
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IS_OMAP_SUBCLASS(543x, 0x543)
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IS_TI_SUBCLASS(816x, 0x816)
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IS_TI_SUBCLASS(814x, 0x814)
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IS_AM_SUBCLASS(335x, 0x335)
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IS_AM_SUBCLASS(437x, 0x437)
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IS_DRA_SUBCLASS(75x, 0x75)
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IS_DRA_SUBCLASS(72x, 0x72)
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#define soc_is_ti81xx() 0
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#define soc_is_ti816x() 0
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#define soc_is_ti814x() 0
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#define soc_is_am35xx() 0
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#define soc_is_am33xx() 0
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#define soc_is_am335x() 0
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#define soc_is_am43xx() 0
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#define soc_is_am437x() 0
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#define soc_is_omap44xx() 0
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#define soc_is_omap443x() 0
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#define soc_is_omap446x() 0
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#define soc_is_omap447x() 0
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#define soc_is_omap54xx() 0
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#define soc_is_omap543x() 0
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#define soc_is_dra7xx() 0
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#define soc_is_dra74x() 0
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#define soc_is_dra72x() 0
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#if defined(CONFIG_ARCH_OMAP2)
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# define soc_is_omap24xx() is_omap24xx()
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#else
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# define soc_is_omap24xx() 0
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#endif
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#if defined(CONFIG_SOC_OMAP2420)
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# define soc_is_omap242x() is_omap242x()
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#else
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# define soc_is_omap242x() 0
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#endif
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#if defined(CONFIG_SOC_OMAP2430)
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# define soc_is_omap243x() is_omap243x()
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#else
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# define soc_is_omap243x() 0
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#endif
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#if defined(CONFIG_ARCH_OMAP3)
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# define soc_is_omap34xx() is_omap34xx()
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# define soc_is_omap343x() is_omap343x()
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#else
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# define soc_is_omap34xx() 0
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# define soc_is_omap343x() 0
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#endif
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/*
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* Macros to detect individual cpu types.
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* These are only rarely needed.
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* soc_is_omap2420(): True for OMAP2420
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* soc_is_omap2422(): True for OMAP2422
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* soc_is_omap2423(): True for OMAP2423
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* soc_is_omap2430(): True for OMAP2430
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* soc_is_omap3430(): True for OMAP3430
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*/
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#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
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#define IS_OMAP_TYPE(type, id) \
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static inline int is_omap ##type (void) \
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{ \
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return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
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}
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IS_OMAP_TYPE(2420, 0x2420)
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IS_OMAP_TYPE(2422, 0x2422)
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IS_OMAP_TYPE(2423, 0x2423)
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IS_OMAP_TYPE(2430, 0x2430)
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IS_OMAP_TYPE(3430, 0x3430)
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#define soc_is_omap2420() 0
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#define soc_is_omap2422() 0
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#define soc_is_omap2423() 0
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#define soc_is_omap2430() 0
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#define soc_is_omap3430() 0
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#define soc_is_omap3630() 0
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#define soc_is_omap5430() 0
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/* These are needed for the common code */
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#define soc_is_omap7xx() 0
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#define soc_is_omap15xx() 0
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#define soc_is_omap16xx() 0
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#define soc_is_omap1510() 0
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#define soc_is_omap1610() 0
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#define soc_is_omap1611() 0
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#define soc_is_omap1621() 0
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#define soc_is_omap1710() 0
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#define cpu_class_is_omap1() 0
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#define cpu_class_is_omap2() 1
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#if defined(CONFIG_ARCH_OMAP2)
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# undef soc_is_omap2420
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# undef soc_is_omap2422
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# undef soc_is_omap2423
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# undef soc_is_omap2430
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# define soc_is_omap2420() is_omap2420()
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# define soc_is_omap2422() is_omap2422()
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# define soc_is_omap2423() is_omap2423()
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# define soc_is_omap2430() is_omap2430()
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#endif
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#if defined(CONFIG_ARCH_OMAP3)
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# undef soc_is_omap3430
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# undef soc_is_ti81xx
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# undef soc_is_ti816x
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# undef soc_is_ti814x
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# undef soc_is_am35xx
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# define soc_is_omap3430() is_omap3430()
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# undef soc_is_omap3630
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# define soc_is_omap3630() is_omap363x()
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# define soc_is_ti81xx() is_ti81xx()
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# define soc_is_ti816x() is_ti816x()
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# define soc_is_ti814x() is_ti814x()
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# define soc_is_am35xx() is_am35xx()
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#endif
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# if defined(CONFIG_SOC_AM33XX)
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# undef soc_is_am33xx
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# undef soc_is_am335x
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# define soc_is_am33xx() is_am33xx()
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# define soc_is_am335x() is_am335x()
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#endif
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#ifdef CONFIG_SOC_AM43XX
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# undef soc_is_am43xx
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# undef soc_is_am437x
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# define soc_is_am43xx() is_am43xx()
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# define soc_is_am437x() is_am437x()
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#endif
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# if defined(CONFIG_ARCH_OMAP4)
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# undef soc_is_omap44xx
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# undef soc_is_omap443x
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# undef soc_is_omap446x
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# undef soc_is_omap447x
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# define soc_is_omap44xx() is_omap44xx()
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# define soc_is_omap443x() is_omap443x()
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# define soc_is_omap446x() is_omap446x()
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# define soc_is_omap447x() is_omap447x()
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# endif
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# if defined(CONFIG_SOC_OMAP5)
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# undef soc_is_omap54xx
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# undef soc_is_omap543x
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# define soc_is_omap54xx() is_omap54xx()
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# define soc_is_omap543x() is_omap543x()
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#endif
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#if defined(CONFIG_SOC_DRA7XX)
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#undef soc_is_dra7xx
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#undef soc_is_dra74x
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#undef soc_is_dra72x
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#define soc_is_dra7xx() is_dra7xx()
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#define soc_is_dra74x() is_dra75x()
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#define soc_is_dra72x() is_dra72x()
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#endif
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/* Various silicon revisions for omap2 */
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#define OMAP242X_CLASS 0x24200024
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#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
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#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
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#define OMAP243X_CLASS 0x24300024
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#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
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#define OMAP343X_CLASS 0x34300034
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#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
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#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
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#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
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#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
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#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
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#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
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#define OMAP363X_CLASS 0x36300034
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#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
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#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
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#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
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#define TI816X_CLASS 0x81600081
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#define TI8168_REV_ES1_0 TI816X_CLASS
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#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
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#define TI8168_REV_ES2_0 (TI816X_CLASS | (0x2 << 8))
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#define TI8168_REV_ES2_1 (TI816X_CLASS | (0x3 << 8))
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#define TI814X_CLASS 0x81400081
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#define TI8148_REV_ES1_0 TI814X_CLASS
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#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
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#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
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#define AM35XX_CLASS 0x35170034
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#define AM35XX_REV_ES1_0 AM35XX_CLASS
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#define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8))
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#define AM335X_CLASS 0x33500033
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#define AM335X_REV_ES1_0 AM335X_CLASS
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#define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8))
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#define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8))
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#define AM437X_CLASS 0x43700000
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#define AM437X_REV_ES1_0 (AM437X_CLASS | (0x10 << 8))
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#define AM437X_REV_ES1_1 (AM437X_CLASS | (0x11 << 8))
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#define AM437X_REV_ES1_2 (AM437X_CLASS | (0x12 << 8))
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#define OMAP443X_CLASS 0x44300044
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#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
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#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
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#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
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#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
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#define OMAP4430_REV_ES2_3 (OMAP443X_CLASS | (0x23 << 8))
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#define OMAP446X_CLASS 0x44600044
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#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
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#define OMAP4460_REV_ES1_1 (OMAP446X_CLASS | (0x11 << 8))
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#define OMAP447X_CLASS 0x44700044
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#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
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#define OMAP54XX_CLASS 0x54000054
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#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
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#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
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#define DRA7XX_CLASS 0x07000000
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#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
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#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
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#define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8))
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#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
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#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
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#define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8))
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void omap2xxx_check_revision(void);
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void omap3xxx_check_revision(void);
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void omap4xxx_check_revision(void);
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void omap5xxx_check_revision(void);
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void dra7xxx_check_revision(void);
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void omap3xxx_check_features(void);
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void ti81xx_check_features(void);
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void am33xx_check_features(void);
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void omap4xxx_check_features(void);
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/*
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* Runtime detection of OMAP3 features
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*
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* OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
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* family have OS-level control over the I/O chain clock. This is
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* to avoid a window during which wakeups could potentially be lost
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* during powerdomain transitions. If this bit is set, it
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* indicates that the chip does support OS-level control of this
|
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* feature.
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*/
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extern u32 omap_features;
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#define OMAP3_HAS_L2CACHE BIT(0)
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#define OMAP3_HAS_IVA BIT(1)
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#define OMAP3_HAS_SGX BIT(2)
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#define OMAP3_HAS_NEON BIT(3)
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#define OMAP3_HAS_ISP BIT(4)
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#define OMAP3_HAS_192MHZ_CLK BIT(5)
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#define OMAP3_HAS_IO_WAKEUP BIT(6)
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#define OMAP3_HAS_SDRC BIT(7)
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#define OMAP3_HAS_IO_CHAIN_CTRL BIT(8)
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#define OMAP4_HAS_PERF_SILICON BIT(9)
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#define OMAP3_HAS_FEATURE(feat,flag) \
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static inline unsigned int omap3_has_ ##feat(void) \
|
|
{ \
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|
return omap_features & OMAP3_HAS_ ##flag; \
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} \
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OMAP3_HAS_FEATURE(l2cache, L2CACHE)
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OMAP3_HAS_FEATURE(sgx, SGX)
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OMAP3_HAS_FEATURE(iva, IVA)
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OMAP3_HAS_FEATURE(neon, NEON)
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OMAP3_HAS_FEATURE(isp, ISP)
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|
OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
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OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
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|
OMAP3_HAS_FEATURE(sdrc, SDRC)
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OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
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|
|
|
/*
|
|
* Runtime detection of OMAP4 features
|
|
*/
|
|
#define OMAP4_HAS_FEATURE(feat, flag) \
|
|
static inline unsigned int omap4_has_ ##feat(void) \
|
|
{ \
|
|
return omap_features & OMAP4_HAS_ ##flag; \
|
|
} \
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|
|
|
OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
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|
|
|
/*
|
|
* We need to make sure omap initcalls don't run when
|
|
* multiplatform kernels are booted on other SoCs.
|
|
*/
|
|
#define omap_initcall(level, fn) \
|
|
static int __init __used __##fn(void) \
|
|
{ \
|
|
if (!soc_is_omap()) \
|
|
return 0; \
|
|
return fn(); \
|
|
} \
|
|
level(__##fn);
|
|
|
|
#define omap_early_initcall(fn) omap_initcall(early_initcall, fn)
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|
#define omap_core_initcall(fn) omap_initcall(core_initcall, fn)
|
|
#define omap_postcore_initcall(fn) omap_initcall(postcore_initcall, fn)
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|
#define omap_arch_initcall(fn) omap_initcall(arch_initcall, fn)
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|
#define omap_subsys_initcall(fn) omap_initcall(subsys_initcall, fn)
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|
#define omap_device_initcall(fn) omap_initcall(device_initcall, fn)
|
|
#define omap_late_initcall(fn) omap_initcall(late_initcall, fn)
|
|
#define omap_late_initcall_sync(fn) omap_initcall(late_initcall_sync, fn)
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|
|
|
/* Legacy defines, these can be removed when users are removed */
|
|
#define cpu_is_omap2420() soc_is_omap2420()
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|
#define cpu_is_omap2422() soc_is_omap2422()
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|
#define cpu_is_omap242x() soc_is_omap242x()
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|
#define cpu_is_omap2430() soc_is_omap2430()
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|
#define cpu_is_omap243x() soc_is_omap243x()
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|
#define cpu_is_omap24xx() soc_is_omap24xx()
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|
#define cpu_is_omap3430() soc_is_omap3430()
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|
#define cpu_is_omap343x() soc_is_omap343x()
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|
#define cpu_is_omap34xx() soc_is_omap34xx()
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|
#define cpu_is_omap3630() soc_is_omap3630()
|
|
#define cpu_is_omap443x() soc_is_omap443x()
|
|
#define cpu_is_omap446x() soc_is_omap446x()
|
|
#define cpu_is_omap44xx() soc_is_omap44xx()
|
|
#define cpu_is_ti814x() soc_is_ti814x()
|
|
#define cpu_is_ti816x() soc_is_ti816x()
|
|
#define cpu_is_ti81xx() soc_is_ti81xx()
|
|
|
|
#endif /* __ASSEMBLY__ */
|