![Kirill A. Shutemov](/assets/img/avatar_default.png)
PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} macros were introduced *long* time ago with promise that one day it will be possible to implement page cache with bigger chunks than PAGE_SIZE. This promise never materialized. And unlikely will. We have many places where PAGE_CACHE_SIZE assumed to be equal to PAGE_SIZE. And it's constant source of confusion on whether PAGE_CACHE_* or PAGE_* constant should be used in a particular case, especially on the border between fs and mm. Global switching to PAGE_CACHE_SIZE != PAGE_SIZE would cause to much breakage to be doable. Let's stop pretending that pages in page cache are special. They are not. The changes are pretty straight-forward: - <foo> << (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>; - <foo> >> (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>; - PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} -> PAGE_{SIZE,SHIFT,MASK,ALIGN}; - page_cache_get() -> get_page(); - page_cache_release() -> put_page(); This patch contains automated changes generated with coccinelle using script below. For some reason, coccinelle doesn't patch header files. I've called spatch for them manually. The only adjustment after coccinelle is revert of changes to PAGE_CAHCE_ALIGN definition: we are going to drop it later. There are few places in the code where coccinelle didn't reach. I'll fix them manually in a separate patch. Comments and documentation also will be addressed with the separate patch. virtual patch @@ expression E; @@ - E << (PAGE_CACHE_SHIFT - PAGE_SHIFT) + E @@ expression E; @@ - E >> (PAGE_CACHE_SHIFT - PAGE_SHIFT) + E @@ @@ - PAGE_CACHE_SHIFT + PAGE_SHIFT @@ @@ - PAGE_CACHE_SIZE + PAGE_SIZE @@ @@ - PAGE_CACHE_MASK + PAGE_MASK @@ expression E; @@ - PAGE_CACHE_ALIGN(E) + PAGE_ALIGN(E) @@ expression E; @@ - page_cache_get(E) + get_page(E) @@ expression E; @@ - page_cache_release(E) + put_page(E) Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Acked-by: Michal Hocko <mhocko@suse.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
632 lines
17 KiB
C
632 lines
17 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
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* Copyright (C) 1999 SuSE GmbH Nuernberg
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* Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
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*
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* Cache and TLB management
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/pagemap.h>
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#include <linux/sched.h>
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#include <asm/pdc.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/shmparam.h>
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int split_tlb __read_mostly;
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int dcache_stride __read_mostly;
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int icache_stride __read_mostly;
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EXPORT_SYMBOL(dcache_stride);
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void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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EXPORT_SYMBOL(flush_dcache_page_asm);
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void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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/* On some machines (e.g. ones with the Merced bus), there can be
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* only a single PxTLB broadcast at a time; this must be guaranteed
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* by software. We put a spinlock around all TLB flushes to
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* ensure this.
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*/
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DEFINE_SPINLOCK(pa_tlb_lock);
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struct pdc_cache_info cache_info __read_mostly;
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#ifndef CONFIG_PA20
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static struct pdc_btlb_info btlb_info __read_mostly;
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#endif
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#ifdef CONFIG_SMP
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void
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flush_data_cache(void)
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{
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on_each_cpu(flush_data_cache_local, NULL, 1);
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}
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void
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flush_instruction_cache(void)
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{
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on_each_cpu(flush_instruction_cache_local, NULL, 1);
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}
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#endif
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void
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flush_cache_all_local(void)
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{
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flush_instruction_cache_local(NULL);
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flush_data_cache_local(NULL);
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}
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EXPORT_SYMBOL(flush_cache_all_local);
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/* Virtual address of pfn. */
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#define pfn_va(pfn) __va(PFN_PHYS(pfn))
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void
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update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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{
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unsigned long pfn = pte_pfn(*ptep);
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struct page *page;
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/* We don't have pte special. As a result, we can be called with
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an invalid pfn and we don't need to flush the kernel dcache page.
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This occurs with FireGL card in C8000. */
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
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flush_kernel_dcache_page_addr(pfn_va(pfn));
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clear_bit(PG_dcache_dirty, &page->flags);
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} else if (parisc_requires_coherency())
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flush_kernel_dcache_page_addr(pfn_va(pfn));
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}
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void
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show_cache_info(struct seq_file *m)
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{
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char buf[32];
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seq_printf(m, "I-cache\t\t: %ld KB\n",
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cache_info.ic_size/1024 );
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if (cache_info.dc_loop != 1)
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snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
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seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
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cache_info.dc_size/1024,
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(cache_info.dc_conf.cc_wt ? "WT":"WB"),
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(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
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((cache_info.dc_loop == 1) ? "direct mapped" : buf));
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seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
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cache_info.it_size,
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cache_info.dt_size,
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cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
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);
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#ifndef CONFIG_PA20
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/* BTLB - Block TLB */
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if (btlb_info.max_size==0) {
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seq_printf(m, "BTLB\t\t: not supported\n" );
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} else {
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seq_printf(m,
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"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
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"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
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"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
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btlb_info.max_size, (int)4096,
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btlb_info.max_size>>8,
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btlb_info.fixed_range_info.num_i,
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btlb_info.fixed_range_info.num_d,
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btlb_info.fixed_range_info.num_comb,
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btlb_info.variable_range_info.num_i,
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btlb_info.variable_range_info.num_d,
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btlb_info.variable_range_info.num_comb
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);
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}
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#endif
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}
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void __init
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parisc_cache_init(void)
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{
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if (pdc_cache_info(&cache_info) < 0)
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panic("parisc_cache_init: pdc_cache_info failed");
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#if 0
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printk("ic_size %lx dc_size %lx it_size %lx\n",
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cache_info.ic_size,
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cache_info.dc_size,
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cache_info.it_size);
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printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.dc_base,
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cache_info.dc_stride,
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cache_info.dc_count,
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cache_info.dc_loop);
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printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.dc_conf),
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cache_info.dc_conf.cc_alias,
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cache_info.dc_conf.cc_block,
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cache_info.dc_conf.cc_line,
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cache_info.dc_conf.cc_shift);
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printk(" wt %d sh %d cst %d hv %d\n",
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cache_info.dc_conf.cc_wt,
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cache_info.dc_conf.cc_sh,
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cache_info.dc_conf.cc_cst,
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cache_info.dc_conf.cc_hv);
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printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.ic_base,
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cache_info.ic_stride,
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cache_info.ic_count,
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cache_info.ic_loop);
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printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
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cache_info.it_sp_base,
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cache_info.it_sp_stride,
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cache_info.it_sp_count,
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cache_info.it_loop,
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cache_info.it_off_base,
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cache_info.it_off_stride,
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cache_info.it_off_count);
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printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
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cache_info.dt_sp_base,
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cache_info.dt_sp_stride,
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cache_info.dt_sp_count,
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cache_info.dt_loop,
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cache_info.dt_off_base,
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cache_info.dt_off_stride,
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cache_info.dt_off_count);
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printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.ic_conf),
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cache_info.ic_conf.cc_alias,
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cache_info.ic_conf.cc_block,
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cache_info.ic_conf.cc_line,
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cache_info.ic_conf.cc_shift);
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printk(" wt %d sh %d cst %d hv %d\n",
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cache_info.ic_conf.cc_wt,
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cache_info.ic_conf.cc_sh,
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cache_info.ic_conf.cc_cst,
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cache_info.ic_conf.cc_hv);
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printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
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cache_info.dt_conf.tc_sh,
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cache_info.dt_conf.tc_page,
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cache_info.dt_conf.tc_cst,
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cache_info.dt_conf.tc_aid,
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cache_info.dt_conf.tc_sr);
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printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
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cache_info.it_conf.tc_sh,
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cache_info.it_conf.tc_page,
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cache_info.it_conf.tc_cst,
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cache_info.it_conf.tc_aid,
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cache_info.it_conf.tc_sr);
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#endif
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split_tlb = 0;
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if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
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if (cache_info.dt_conf.tc_sh == 2)
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printk(KERN_WARNING "Unexpected TLB configuration. "
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"Will flush I/D separately (could be optimized).\n");
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split_tlb = 1;
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}
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/* "New and Improved" version from Jim Hull
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* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
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* The following CAFL_STRIDE is an optimized version, see
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
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*/
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#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
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dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
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icache_stride = CAFL_STRIDE(cache_info.ic_conf);
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#undef CAFL_STRIDE
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#ifndef CONFIG_PA20
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if (pdc_btlb_info(&btlb_info) < 0) {
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memset(&btlb_info, 0, sizeof btlb_info);
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}
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#endif
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if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
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PDC_MODEL_NVA_UNSUPPORTED) {
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printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
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#if 0
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panic("SMP kernel required to avoid non-equivalent aliasing");
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#endif
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}
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}
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void disable_sr_hashing(void)
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{
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int srhash_type, retval;
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unsigned long space_bits;
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switch (boot_cpu_data.cpu_type) {
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case pcx: /* We shouldn't get this far. setup.c should prevent it. */
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BUG();
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return;
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case pcxs:
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case pcxt:
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case pcxt_:
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srhash_type = SRHASH_PCXST;
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break;
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case pcxl:
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srhash_type = SRHASH_PCXL;
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break;
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case pcxl2: /* pcxl2 doesn't support space register hashing */
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return;
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default: /* Currently all PA2.0 machines use the same ins. sequence */
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srhash_type = SRHASH_PA20;
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break;
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}
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disable_sr_hashing_asm(srhash_type);
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retval = pdc_spaceid_bits(&space_bits);
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/* If this procedure isn't implemented, don't panic. */
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if (retval < 0 && retval != PDC_BAD_OPTION)
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panic("pdc_spaceid_bits call failed.\n");
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if (space_bits != 0)
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panic("SpaceID hashing is still on!\n");
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}
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static inline void
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__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
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unsigned long physaddr)
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{
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preempt_disable();
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flush_dcache_page_asm(physaddr, vmaddr);
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if (vma->vm_flags & VM_EXEC)
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flush_icache_page_asm(physaddr, vmaddr);
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preempt_enable();
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}
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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struct vm_area_struct *mpnt;
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unsigned long offset;
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unsigned long addr, old_addr = 0;
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pgoff_t pgoff;
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if (mapping && !mapping_mapped(mapping)) {
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set_bit(PG_dcache_dirty, &page->flags);
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return;
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}
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flush_kernel_dcache_page(page);
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if (!mapping)
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return;
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pgoff = page->index;
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/* We have carefully arranged in arch_get_unmapped_area() that
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* *any* mappings of a file are always congruently mapped (whether
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* declared as MAP_PRIVATE or MAP_SHARED), so we only need
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* to flush one address here for them all to become coherent */
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flush_dcache_mmap_lock(mapping);
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vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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addr = mpnt->vm_start + offset;
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/* The TLB is the engine of coherence on parisc: The
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* CPU is entitled to speculate any page with a TLB
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* mapping, so here we kill the mapping then flush the
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* page along a special flush only alias mapping.
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* This guarantees that the page is no-longer in the
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* cache for any process and nor may it be
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* speculatively read in (until the user or kernel
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* specifically accesses it, of course) */
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flush_tlb_page(mpnt, addr);
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if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
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!= (addr & (SHM_COLOUR - 1))) {
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__flush_cache_page(mpnt, addr, page_to_phys(page));
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if (old_addr)
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printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
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old_addr = addr;
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}
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}
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flush_dcache_mmap_unlock(mapping);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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/* Defined in arch/parisc/kernel/pacache.S */
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EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
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EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
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EXPORT_SYMBOL(flush_data_cache_local);
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EXPORT_SYMBOL(flush_kernel_icache_range_asm);
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#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
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static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
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#define FLUSH_TLB_THRESHOLD (2*1024*1024) /* 2MB initial TLB threshold */
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static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD;
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void __init parisc_setup_cache_timing(void)
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{
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unsigned long rangetime, alltime;
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unsigned long size, start;
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alltime = mfctl(16);
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flush_data_cache();
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alltime = mfctl(16) - alltime;
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size = (unsigned long)(_end - _text);
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rangetime = mfctl(16);
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flush_kernel_dcache_range((unsigned long)_text, size);
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rangetime = mfctl(16) - rangetime;
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printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
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alltime, size, rangetime);
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/* Racy, but if we see an intermediate value, it's ok too... */
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parisc_cache_flush_threshold = size * alltime / rangetime;
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parisc_cache_flush_threshold = L1_CACHE_ALIGN(parisc_cache_flush_threshold);
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if (!parisc_cache_flush_threshold)
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parisc_cache_flush_threshold = FLUSH_THRESHOLD;
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if (parisc_cache_flush_threshold > cache_info.dc_size)
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parisc_cache_flush_threshold = cache_info.dc_size;
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printk(KERN_INFO "Setting cache flush threshold to %lu kB\n",
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parisc_cache_flush_threshold/1024);
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/* calculate TLB flush threshold */
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alltime = mfctl(16);
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flush_tlb_all();
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alltime = mfctl(16) - alltime;
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size = PAGE_SIZE;
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start = (unsigned long) _text;
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rangetime = mfctl(16);
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while (start < (unsigned long) _end) {
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flush_tlb_kernel_range(start, start + PAGE_SIZE);
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start += PAGE_SIZE;
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size += PAGE_SIZE;
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}
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rangetime = mfctl(16) - rangetime;
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printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n",
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alltime, size, rangetime);
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parisc_tlb_flush_threshold = size * alltime / rangetime;
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parisc_tlb_flush_threshold *= num_online_cpus();
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parisc_tlb_flush_threshold = PAGE_ALIGN(parisc_tlb_flush_threshold);
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if (!parisc_tlb_flush_threshold)
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parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
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printk(KERN_INFO "Setting TLB flush threshold to %lu kB\n",
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parisc_tlb_flush_threshold/1024);
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}
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extern void purge_kernel_dcache_page_asm(unsigned long);
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extern void clear_user_page_asm(void *, unsigned long);
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extern void copy_user_page_asm(void *, void *, unsigned long);
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void flush_kernel_dcache_page_addr(void *addr)
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{
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unsigned long flags;
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flush_kernel_dcache_page_asm(addr);
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purge_tlb_start(flags);
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pdtlb_kernel(addr);
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purge_tlb_end(flags);
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}
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EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
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void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
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struct page *pg)
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{
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/* Copy using kernel mapping. No coherency is needed (all in
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kunmap) for the `to' page. However, the `from' page needs to
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be flushed through a mapping equivalent to the user mapping
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before it can be accessed through the kernel mapping. */
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preempt_disable();
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flush_dcache_page_asm(__pa(vfrom), vaddr);
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preempt_enable();
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copy_page_asm(vto, vfrom);
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}
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EXPORT_SYMBOL(copy_user_page);
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/* __flush_tlb_range()
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*
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* returns 1 if all TLBs were flushed.
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*/
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int __flush_tlb_range(unsigned long sid, unsigned long start,
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unsigned long end)
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{
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unsigned long flags, size;
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size = (end - start);
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if (size >= parisc_tlb_flush_threshold) {
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flush_tlb_all();
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return 1;
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}
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/* Purge TLB entries for small ranges using the pdtlb and
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pitlb instructions. These instructions execute locally
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but cause a purge request to be broadcast to other TLBs. */
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if (likely(!split_tlb)) {
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while (start < end) {
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purge_tlb_start(flags);
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mtsp(sid, 1);
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pdtlb(start);
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purge_tlb_end(flags);
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start += PAGE_SIZE;
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}
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return 0;
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}
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/* split TLB case */
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while (start < end) {
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purge_tlb_start(flags);
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mtsp(sid, 1);
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pdtlb(start);
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pitlb(start);
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purge_tlb_end(flags);
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start += PAGE_SIZE;
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}
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return 0;
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}
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static void cacheflush_h_tmp_function(void *dummy)
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{
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flush_cache_all_local();
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}
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void flush_cache_all(void)
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{
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on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
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}
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static inline unsigned long mm_total_size(struct mm_struct *mm)
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{
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struct vm_area_struct *vma;
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unsigned long usize = 0;
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for (vma = mm->mmap; vma; vma = vma->vm_next)
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usize += vma->vm_end - vma->vm_start;
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return usize;
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}
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static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
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{
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pte_t *ptep = NULL;
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if (!pgd_none(*pgd)) {
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pud_t *pud = pud_offset(pgd, addr);
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if (!pud_none(*pud)) {
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pmd_t *pmd = pmd_offset(pud, addr);
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if (!pmd_none(*pmd))
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ptep = pte_offset_map(pmd, addr);
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}
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}
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return ptep;
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}
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void flush_cache_mm(struct mm_struct *mm)
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{
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struct vm_area_struct *vma;
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pgd_t *pgd;
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/* Flushing the whole cache on each cpu takes forever on
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rp3440, etc. So, avoid it if the mm isn't too big. */
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if (mm_total_size(mm) >= parisc_cache_flush_threshold) {
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flush_cache_all();
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return;
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}
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if (mm->context == mfsp(3)) {
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for (vma = mm->mmap; vma; vma = vma->vm_next) {
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flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
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if ((vma->vm_flags & VM_EXEC) == 0)
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continue;
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flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
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}
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return;
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}
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pgd = mm->pgd;
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for (vma = mm->mmap; vma; vma = vma->vm_next) {
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unsigned long addr;
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for (addr = vma->vm_start; addr < vma->vm_end;
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addr += PAGE_SIZE) {
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unsigned long pfn;
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pte_t *ptep = get_ptep(pgd, addr);
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if (!ptep)
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continue;
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pfn = pte_pfn(*ptep);
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if (!pfn_valid(pfn))
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continue;
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__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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}
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}
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}
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void
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flush_user_dcache_range(unsigned long start, unsigned long end)
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{
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if ((end - start) < parisc_cache_flush_threshold)
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flush_user_dcache_range_asm(start,end);
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else
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flush_data_cache();
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}
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void
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flush_user_icache_range(unsigned long start, unsigned long end)
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{
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if ((end - start) < parisc_cache_flush_threshold)
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flush_user_icache_range_asm(start,end);
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else
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flush_instruction_cache();
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}
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void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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unsigned long addr;
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pgd_t *pgd;
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BUG_ON(!vma->vm_mm->context);
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if ((end - start) >= parisc_cache_flush_threshold) {
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flush_cache_all();
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return;
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}
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if (vma->vm_mm->context == mfsp(3)) {
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flush_user_dcache_range_asm(start, end);
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if (vma->vm_flags & VM_EXEC)
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flush_user_icache_range_asm(start, end);
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return;
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}
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pgd = vma->vm_mm->pgd;
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for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
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unsigned long pfn;
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pte_t *ptep = get_ptep(pgd, addr);
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if (!ptep)
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continue;
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pfn = pte_pfn(*ptep);
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if (pfn_valid(pfn))
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__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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}
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}
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void
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flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
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{
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BUG_ON(!vma->vm_mm->context);
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if (pfn_valid(pfn)) {
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flush_tlb_page(vma, vmaddr);
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__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
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}
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}
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