dee89c4d94
Liam Girdwood's ASoC v2 work avoids having two different ops structures for DAIs by merging the members of struct snd_soc_ops into struct snd_soc_dai_ops, allowing per DAI configuration for everything. Backport this change. This paves the way for future work allowing any combination of DAIs to be connected rather than having fixed purpose CODEC and CPU DAIs and only allowing CODEC<->CPU interconnections. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
488 lines
14 KiB
C
488 lines
14 KiB
C
/*
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* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
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*
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* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
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* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include "davinci-pcm.h"
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#define DAVINCI_MCBSP_DRR_REG 0x00
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#define DAVINCI_MCBSP_DXR_REG 0x04
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#define DAVINCI_MCBSP_SPCR_REG 0x08
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#define DAVINCI_MCBSP_RCR_REG 0x0c
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#define DAVINCI_MCBSP_XCR_REG 0x10
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#define DAVINCI_MCBSP_SRGR_REG 0x14
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#define DAVINCI_MCBSP_PCR_REG 0x24
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#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
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#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
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#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
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#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
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#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
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#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
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#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
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#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
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#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
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#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
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#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
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#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
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#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
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#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
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#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
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#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
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#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
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#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
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#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
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#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
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#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
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#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
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#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
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#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
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#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
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#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
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#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
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#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
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#define MOD_REG_BIT(val, mask, set) do { \
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if (set) { \
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val |= mask; \
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} else { \
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val &= ~mask; \
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} \
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} while (0)
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enum {
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DAVINCI_MCBSP_WORD_8 = 0,
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DAVINCI_MCBSP_WORD_12,
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DAVINCI_MCBSP_WORD_16,
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DAVINCI_MCBSP_WORD_20,
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DAVINCI_MCBSP_WORD_24,
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DAVINCI_MCBSP_WORD_32,
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};
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static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
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.name = "I2S PCM Stereo out",
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};
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static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
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.name = "I2S PCM Stereo in",
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};
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struct davinci_mcbsp_dev {
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void __iomem *base;
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struct clk *clk;
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struct davinci_pcm_dma_params *dma_params[2];
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};
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static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
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int reg, u32 val)
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{
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__raw_writel(val, dev->base + reg);
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}
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static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
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{
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return __raw_readl(dev->base + reg);
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}
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static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_platform *platform = socdev->platform;
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u32 w;
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int ret;
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/* Start the sample generator and enable transmitter/receiver */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/* Stop the DMA to avoid data loss */
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/* while the transmitter is out of reset to handle XSYNCERR */
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if (platform->pcm_ops->trigger) {
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ret = platform->pcm_ops->trigger(substream,
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SNDRV_PCM_TRIGGER_STOP);
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if (ret < 0)
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printk(KERN_DEBUG "Playback DMA stop failed\n");
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}
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/* Enable the transmitter */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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/* wait for any unexpected frame sync error to occur */
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udelay(100);
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/* Disable the transmitter to clear any outstanding XSYNCERR */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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/* Restart the DMA */
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if (platform->pcm_ops->trigger) {
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ret = platform->pcm_ops->trigger(substream,
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SNDRV_PCM_TRIGGER_START);
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if (ret < 0)
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printk(KERN_DEBUG "Playback DMA start failed\n");
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}
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/* Enable the transmitter */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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} else {
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/* Enable the reciever */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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}
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/* Start frame sync */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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}
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static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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u32 w;
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/* Reset transmitter/receiver and sample rate/frame sync generators */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
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DAVINCI_MCBSP_SPCR_FRST, 0);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
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else
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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}
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static int davinci_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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cpu_dai->dma_data = dev->dma_params[substream->stream];
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return 0;
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}
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static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
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u32 w;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
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DAVINCI_MCBSP_PCR_FSXM |
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DAVINCI_MCBSP_PCR_FSRM |
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DAVINCI_MCBSP_PCR_CLKXM |
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DAVINCI_MCBSP_PCR_CLKRM);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
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DAVINCI_MCBSP_SRGR_FSGM);
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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/* McBSP CLKR pin is the input for the Sample Rate Generator.
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* McBSP FSR and FSX are driven by the Sample Rate Generator. */
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
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DAVINCI_MCBSP_PCR_SCLKME |
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DAVINCI_MCBSP_PCR_FSXM |
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DAVINCI_MCBSP_PCR_FSRM);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
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DAVINCI_MCBSP_SRGR_FSGM);
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_IB_NF:
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
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DAVINCI_MCBSP_PCR_CLKRP, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
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break;
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case SND_SOC_DAIFMT_NB_IF:
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
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DAVINCI_MCBSP_PCR_FSRP, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
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break;
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case SND_SOC_DAIFMT_IB_IF:
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
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DAVINCI_MCBSP_PCR_CLKRP |
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DAVINCI_MCBSP_PCR_FSXP |
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DAVINCI_MCBSP_PCR_FSRP, 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
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break;
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case SND_SOC_DAIFMT_NB_NF:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_RIGHT_J:
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
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DAVINCI_MCBSP_RCR_RFRLEN1(1) |
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DAVINCI_MCBSP_RCR_RDATDLY(0));
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
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DAVINCI_MCBSP_XCR_XFRLEN1(1) |
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DAVINCI_MCBSP_XCR_XDATDLY(0) |
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DAVINCI_MCBSP_XCR_XFIG);
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break;
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case SND_SOC_DAIFMT_I2S:
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default:
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
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DAVINCI_MCBSP_RCR_RFRLEN1(1) |
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DAVINCI_MCBSP_RCR_RDATDLY(1));
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
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DAVINCI_MCBSP_XCR_XFRLEN1(1) |
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DAVINCI_MCBSP_XCR_XDATDLY(1) |
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DAVINCI_MCBSP_XCR_XFIG);
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break;
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}
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return 0;
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}
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static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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struct snd_interval *i = NULL;
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int mcbsp_word_length;
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u32 w;
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/* general line settings */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
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w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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} else {
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w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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}
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i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
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i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
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/* Determine xfer data type */
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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dma_params->data_type = 1;
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mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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dma_params->data_type = 2;
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mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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dma_params->data_type = 4;
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mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
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break;
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default:
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printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
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DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
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} else {
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
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DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
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}
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return 0;
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}
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static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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davinci_mcbsp_start(substream);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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davinci_mcbsp_stop(substream);
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int davinci_i2s_probe(struct platform_device *pdev,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_device *socdev = platform_get_drvdata(pdev);
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struct snd_soc_card *card = socdev->card;
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struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
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struct davinci_mcbsp_dev *dev;
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struct resource *mem, *ioarea;
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struct evm_snd_platform_data *pdata;
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int ret;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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|
if (!mem) {
|
|
dev_err(&pdev->dev, "no mem resource?\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
|
|
pdev->name);
|
|
if (!ioarea) {
|
|
dev_err(&pdev->dev, "McBSP region already claimed\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
|
|
if (!dev) {
|
|
ret = -ENOMEM;
|
|
goto err_release_region;
|
|
}
|
|
|
|
cpu_dai->private_data = dev;
|
|
|
|
dev->clk = clk_get(&pdev->dev, "McBSPCLK");
|
|
if (IS_ERR(dev->clk)) {
|
|
ret = -ENODEV;
|
|
goto err_free_mem;
|
|
}
|
|
clk_enable(dev->clk);
|
|
|
|
dev->base = (void __iomem *)IO_ADDRESS(mem->start);
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
|
|
dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
|
|
dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
|
|
(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
|
|
|
|
dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
|
|
dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
|
|
dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
|
|
(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
|
|
|
|
return 0;
|
|
|
|
err_free_mem:
|
|
kfree(dev);
|
|
err_release_region:
|
|
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void davinci_i2s_remove(struct platform_device *pdev,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
|
|
struct snd_soc_card *card = socdev->card;
|
|
struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
|
|
struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
|
|
struct resource *mem;
|
|
|
|
clk_disable(dev->clk);
|
|
clk_put(dev->clk);
|
|
dev->clk = NULL;
|
|
|
|
kfree(dev);
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
|
}
|
|
|
|
#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
|
|
|
|
struct snd_soc_dai davinci_i2s_dai = {
|
|
.name = "davinci-i2s",
|
|
.id = 0,
|
|
.type = SND_SOC_DAI_I2S,
|
|
.probe = davinci_i2s_probe,
|
|
.remove = davinci_i2s_remove,
|
|
.playback = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = DAVINCI_I2S_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
|
|
.capture = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.rates = DAVINCI_I2S_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
|
|
.ops = {
|
|
.startup = davinci_i2s_startup,
|
|
.trigger = davinci_i2s_trigger,
|
|
.hw_params = davinci_i2s_hw_params,
|
|
.set_fmt = davinci_i2s_set_dai_fmt,
|
|
},
|
|
};
|
|
EXPORT_SYMBOL_GPL(davinci_i2s_dai);
|
|
|
|
MODULE_AUTHOR("Vladimir Barinov");
|
|
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
|
|
MODULE_LICENSE("GPL");
|