![Tim Schmielau](/assets/img/avatar_default.png)
After Al Viro (finally) succeeded in removing the sched.h #include in module.h recently, it makes sense again to remove other superfluous sched.h includes. There are quite a lot of files which include it but don't actually need anything defined in there. Presumably these includes were once needed for macros that used to live in sched.h, but moved to other header files in the course of cleaning it up. To ease the pain, this time I did not fiddle with any header files and only removed #includes from .c-files, which tend to cause less trouble. Compile tested against 2.6.20-rc2 and 2.6.20-rc2-mm2 (with offsets) on alpha, arm, i386, ia64, mips, powerpc, and x86_64 with allnoconfig, defconfig, allmodconfig, and allyesconfig as well as a few randconfigs on x86_64 and all configs in arch/arm/configs on arm. I also checked that no new warnings were introduced by the patch (actually, some warnings are removed that were emitted by unnecessarily included header files). Signed-off-by: Tim Schmielau <tim@physik3.uni-rostock.de> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
423 lines
11 KiB
C
423 lines
11 KiB
C
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/*
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* ATI Mach64 Hardware Acceleration
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*/
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <video/mach64.h>
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#include "atyfb.h"
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/*
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* Generic Mach64 routines
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*/
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/* this is for DMA GUI engine! work in progress */
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typedef struct {
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u32 frame_buf_offset;
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u32 system_mem_addr;
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u32 command;
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u32 reserved;
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} BM_DESCRIPTOR_ENTRY;
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#define LAST_DESCRIPTOR (1 << 31)
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#define SYSTEM_TO_FRAME_BUFFER 0
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static u32 rotation24bpp(u32 dx, u32 direction)
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{
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u32 rotation;
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if (direction & DST_X_LEFT_TO_RIGHT) {
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rotation = (dx / 4) % 6;
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} else {
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rotation = ((dx + 2) / 4) % 6;
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}
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return ((rotation << 8) | DST_24_ROTATION_ENABLE);
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}
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void aty_reset_engine(const struct atyfb_par *par)
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{
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/* reset engine */
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aty_st_le32(GEN_TEST_CNTL,
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aty_ld_le32(GEN_TEST_CNTL, par) & ~GUI_ENGINE_ENABLE, par);
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/* enable engine */
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aty_st_le32(GEN_TEST_CNTL,
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aty_ld_le32(GEN_TEST_CNTL, par) | GUI_ENGINE_ENABLE, par);
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/* ensure engine is not locked up by clearing any FIFO or */
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/* HOST errors */
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aty_st_le32(BUS_CNTL,
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aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par);
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}
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static void reset_GTC_3D_engine(const struct atyfb_par *par)
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{
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aty_st_le32(SCALE_3D_CNTL, 0xc0, par);
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mdelay(GTC_3D_RESET_DELAY);
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aty_st_le32(SETUP_CNTL, 0x00, par);
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mdelay(GTC_3D_RESET_DELAY);
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aty_st_le32(SCALE_3D_CNTL, 0x00, par);
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mdelay(GTC_3D_RESET_DELAY);
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}
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void aty_init_engine(struct atyfb_par *par, struct fb_info *info)
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{
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u32 pitch_value;
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/* determine modal information from global mode structure */
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pitch_value = info->var.xres_virtual;
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if (info->var.bits_per_pixel == 24) {
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/* In 24 bpp, the engine is in 8 bpp - this requires that all */
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/* horizontal coordinates and widths must be adjusted */
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pitch_value *= 3;
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}
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/* On GTC (RagePro), we need to reset the 3D engine before */
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if (M64_HAS(RESET_3D))
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reset_GTC_3D_engine(par);
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/* Reset engine, enable, and clear any engine errors */
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aty_reset_engine(par);
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/* Ensure that vga page pointers are set to zero - the upper */
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/* page pointers are set to 1 to handle overflows in the */
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/* lower page */
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aty_st_le32(MEM_VGA_WP_SEL, 0x00010000, par);
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aty_st_le32(MEM_VGA_RP_SEL, 0x00010000, par);
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/* ---- Setup standard engine context ---- */
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/* All GUI registers here are FIFOed - therefore, wait for */
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/* the appropriate number of empty FIFO entries */
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wait_for_fifo(14, par);
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/* enable all registers to be loaded for context loads */
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aty_st_le32(CONTEXT_MASK, 0xFFFFFFFF, par);
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/* set destination pitch to modal pitch, set offset to zero */
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aty_st_le32(DST_OFF_PITCH, (pitch_value / 8) << 22, par);
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/* zero these registers (set them to a known state) */
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aty_st_le32(DST_Y_X, 0, par);
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aty_st_le32(DST_HEIGHT, 0, par);
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aty_st_le32(DST_BRES_ERR, 0, par);
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aty_st_le32(DST_BRES_INC, 0, par);
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aty_st_le32(DST_BRES_DEC, 0, par);
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/* set destination drawing attributes */
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aty_st_le32(DST_CNTL, DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
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DST_X_LEFT_TO_RIGHT, par);
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/* set source pitch to modal pitch, set offset to zero */
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aty_st_le32(SRC_OFF_PITCH, (pitch_value / 8) << 22, par);
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/* set these registers to a known state */
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aty_st_le32(SRC_Y_X, 0, par);
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aty_st_le32(SRC_HEIGHT1_WIDTH1, 1, par);
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aty_st_le32(SRC_Y_X_START, 0, par);
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aty_st_le32(SRC_HEIGHT2_WIDTH2, 1, par);
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/* set source pixel retrieving attributes */
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aty_st_le32(SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT, par);
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/* set host attributes */
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wait_for_fifo(13, par);
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aty_st_le32(HOST_CNTL, 0, par);
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/* set pattern attributes */
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aty_st_le32(PAT_REG0, 0, par);
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aty_st_le32(PAT_REG1, 0, par);
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aty_st_le32(PAT_CNTL, 0, par);
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/* set scissors to modal size */
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aty_st_le32(SC_LEFT, 0, par);
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aty_st_le32(SC_TOP, 0, par);
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aty_st_le32(SC_BOTTOM, par->crtc.vyres - 1, par);
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aty_st_le32(SC_RIGHT, pitch_value - 1, par);
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/* set background color to minimum value (usually BLACK) */
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aty_st_le32(DP_BKGD_CLR, 0, par);
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/* set foreground color to maximum value (usually WHITE) */
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aty_st_le32(DP_FRGD_CLR, 0xFFFFFFFF, par);
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/* set write mask to effect all pixel bits */
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aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF, par);
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/* set foreground mix to overpaint and background mix to */
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/* no-effect */
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aty_st_le32(DP_MIX, FRGD_MIX_S | BKGD_MIX_D, par);
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/* set primary source pixel channel to foreground color */
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/* register */
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aty_st_le32(DP_SRC, FRGD_SRC_FRGD_CLR, par);
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/* set compare functionality to false (no-effect on */
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/* destination) */
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wait_for_fifo(3, par);
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aty_st_le32(CLR_CMP_CLR, 0, par);
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aty_st_le32(CLR_CMP_MASK, 0xFFFFFFFF, par);
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aty_st_le32(CLR_CMP_CNTL, 0, par);
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/* set pixel depth */
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wait_for_fifo(2, par);
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aty_st_le32(DP_PIX_WIDTH, par->crtc.dp_pix_width, par);
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aty_st_le32(DP_CHAIN_MASK, par->crtc.dp_chain_mask, par);
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wait_for_fifo(5, par);
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aty_st_le32(SCALE_3D_CNTL, 0, par);
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aty_st_le32(Z_CNTL, 0, par);
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aty_st_le32(CRTC_INT_CNTL, aty_ld_le32(CRTC_INT_CNTL, par) & ~0x20,
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par);
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aty_st_le32(GUI_TRAJ_CNTL, 0x100023, par);
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/* insure engine is idle before leaving */
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wait_for_idle(par);
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}
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/*
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* Accelerated functions
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*/
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static inline void draw_rect(s16 x, s16 y, u16 width, u16 height,
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struct atyfb_par *par)
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{
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/* perform rectangle fill */
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wait_for_fifo(2, par);
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aty_st_le32(DST_Y_X, (x << 16) | y, par);
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aty_st_le32(DST_HEIGHT_WIDTH, (width << 16) | height, par);
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par->blitter_may_be_busy = 1;
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}
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void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
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{
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struct atyfb_par *par = (struct atyfb_par *) info->par;
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u32 dy = area->dy, sy = area->sy, direction = DST_LAST_PEL;
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u32 sx = area->sx, dx = area->dx, width = area->width, rotation = 0;
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if (par->asleep)
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return;
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if (!area->width || !area->height)
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return;
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if (!par->accel_flags) {
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cfb_copyarea(info, area);
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return;
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}
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if (info->var.bits_per_pixel == 24) {
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/* In 24 bpp, the engine is in 8 bpp - this requires that all */
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/* horizontal coordinates and widths must be adjusted */
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sx *= 3;
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dx *= 3;
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width *= 3;
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}
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if (area->sy < area->dy) {
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dy += area->height - 1;
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sy += area->height - 1;
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} else
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direction |= DST_Y_TOP_TO_BOTTOM;
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if (sx < dx) {
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dx += width - 1;
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sx += width - 1;
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} else
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direction |= DST_X_LEFT_TO_RIGHT;
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if (info->var.bits_per_pixel == 24) {
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rotation = rotation24bpp(dx, direction);
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}
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wait_for_fifo(4, par);
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aty_st_le32(DP_SRC, FRGD_SRC_BLIT, par);
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aty_st_le32(SRC_Y_X, (sx << 16) | sy, par);
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aty_st_le32(SRC_HEIGHT1_WIDTH1, (width << 16) | area->height, par);
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aty_st_le32(DST_CNTL, direction | rotation, par);
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draw_rect(dx, dy, width, area->height, par);
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}
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void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
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{
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struct atyfb_par *par = (struct atyfb_par *) info->par;
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u32 color = rect->color, dx = rect->dx, width = rect->width, rotation = 0;
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if (par->asleep)
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return;
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if (!rect->width || !rect->height)
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return;
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if (!par->accel_flags) {
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cfb_fillrect(info, rect);
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return;
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}
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color |= (rect->color << 8);
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color |= (rect->color << 16);
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if (info->var.bits_per_pixel == 24) {
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/* In 24 bpp, the engine is in 8 bpp - this requires that all */
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/* horizontal coordinates and widths must be adjusted */
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dx *= 3;
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width *= 3;
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rotation = rotation24bpp(dx, DST_X_LEFT_TO_RIGHT);
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}
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wait_for_fifo(3, par);
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aty_st_le32(DP_FRGD_CLR, color, par);
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aty_st_le32(DP_SRC,
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BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR | MONO_SRC_ONE,
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par);
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aty_st_le32(DST_CNTL,
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DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
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DST_X_LEFT_TO_RIGHT | rotation, par);
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draw_rect(dx, rect->dy, width, rect->height, par);
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}
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void atyfb_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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struct atyfb_par *par = (struct atyfb_par *) info->par;
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u32 src_bytes, dx = image->dx, dy = image->dy, width = image->width;
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u32 pix_width_save, pix_width, host_cntl, rotation = 0, src, mix;
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if (par->asleep)
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return;
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if (!image->width || !image->height)
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return;
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if (!par->accel_flags ||
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(image->depth != 1 && info->var.bits_per_pixel != image->depth)) {
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cfb_imageblit(info, image);
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return;
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}
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pix_width = pix_width_save = aty_ld_le32(DP_PIX_WIDTH, par);
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host_cntl = aty_ld_le32(HOST_CNTL, par) | HOST_BYTE_ALIGN;
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switch (image->depth) {
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case 1:
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pix_width &= ~(BYTE_ORDER_MASK | HOST_MASK);
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pix_width |= (BYTE_ORDER_MSB_TO_LSB | HOST_1BPP);
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break;
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case 4:
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pix_width &= ~(BYTE_ORDER_MASK | HOST_MASK);
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pix_width |= (BYTE_ORDER_MSB_TO_LSB | HOST_4BPP);
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break;
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case 8:
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pix_width &= ~HOST_MASK;
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pix_width |= HOST_8BPP;
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break;
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case 15:
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pix_width &= ~HOST_MASK;
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pix_width |= HOST_15BPP;
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break;
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case 16:
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pix_width &= ~HOST_MASK;
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pix_width |= HOST_16BPP;
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break;
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case 24:
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pix_width &= ~HOST_MASK;
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pix_width |= HOST_24BPP;
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break;
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case 32:
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pix_width &= ~HOST_MASK;
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pix_width |= HOST_32BPP;
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break;
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}
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if (info->var.bits_per_pixel == 24) {
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/* In 24 bpp, the engine is in 8 bpp - this requires that all */
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/* horizontal coordinates and widths must be adjusted */
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dx *= 3;
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width *= 3;
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rotation = rotation24bpp(dx, DST_X_LEFT_TO_RIGHT);
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pix_width &= ~DST_MASK;
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pix_width |= DST_8BPP;
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/*
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* since Rage 3D IIc we have DP_HOST_TRIPLE_EN bit
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* this hwaccelerated triple has an issue with not aligned data
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*/
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if (M64_HAS(HW_TRIPLE) && image->width % 8 == 0)
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pix_width |= DP_HOST_TRIPLE_EN;
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}
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if (image->depth == 1) {
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u32 fg, bg;
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if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
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info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
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fg = ((u32*)(info->pseudo_palette))[image->fg_color];
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bg = ((u32*)(info->pseudo_palette))[image->bg_color];
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} else {
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fg = image->fg_color;
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bg = image->bg_color;
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}
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wait_for_fifo(2, par);
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aty_st_le32(DP_BKGD_CLR, bg, par);
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aty_st_le32(DP_FRGD_CLR, fg, par);
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src = MONO_SRC_HOST | FRGD_SRC_FRGD_CLR | BKGD_SRC_BKGD_CLR;
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mix = FRGD_MIX_S | BKGD_MIX_S;
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} else {
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src = MONO_SRC_ONE | FRGD_SRC_HOST;
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mix = FRGD_MIX_D_XOR_S | BKGD_MIX_D;
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}
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wait_for_fifo(6, par);
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aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF, par);
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aty_st_le32(DP_PIX_WIDTH, pix_width, par);
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aty_st_le32(DP_MIX, mix, par);
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aty_st_le32(DP_SRC, src, par);
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aty_st_le32(HOST_CNTL, host_cntl, par);
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aty_st_le32(DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT | rotation, par);
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draw_rect(dx, dy, width, image->height, par);
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src_bytes = (((image->width * image->depth) + 7) / 8) * image->height;
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/* manual triple each pixel */
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if (info->var.bits_per_pixel == 24 && !(pix_width & DP_HOST_TRIPLE_EN)) {
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int inbit, outbit, mult24, byte_id_in_dword, width;
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u8 *pbitmapin = (u8*)image->data, *pbitmapout;
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u32 hostdword;
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for (width = image->width, inbit = 7, mult24 = 0; src_bytes; ) {
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for (hostdword = 0, pbitmapout = (u8*)&hostdword, byte_id_in_dword = 0;
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byte_id_in_dword < 4 && src_bytes;
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byte_id_in_dword++, pbitmapout++) {
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for (outbit = 7; outbit >= 0; outbit--) {
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*pbitmapout |= (((*pbitmapin >> inbit) & 1) << outbit);
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mult24++;
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/* next bit */
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if (mult24 == 3) {
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mult24 = 0;
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inbit--;
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width--;
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}
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/* next byte */
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if (inbit < 0 || width == 0) {
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src_bytes--;
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pbitmapin++;
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inbit = 7;
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if (width == 0) {
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width = image->width;
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outbit = 0;
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}
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}
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}
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}
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wait_for_fifo(1, par);
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aty_st_le32(HOST_DATA0, hostdword, par);
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}
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} else {
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u32 *pbitmap, dwords = (src_bytes + 3) / 4;
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for (pbitmap = (u32*)(image->data); dwords; dwords--, pbitmap++) {
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wait_for_fifo(1, par);
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aty_st_le32(HOST_DATA0, le32_to_cpup(pbitmap), par);
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}
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}
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/* restore pix_width */
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wait_for_fifo(1, par);
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aty_st_le32(DP_PIX_WIDTH, pix_width_save, par);
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}
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