569 lines
14 KiB
C
569 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Mobiveil PCIe Endpoint controller driver
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*
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* Copyright 2019 NXP
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* Author: Xiaowei Bao <xiaowei.bao@nxp.com>
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*/
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#include <linux/of.h>
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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#include <linux/platform_device.h>
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#include "pcie-mobiveil.h"
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static void mobiveil_pcie_ep_func_select(struct mobiveil_pcie *pcie, u8 func_no)
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{
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u32 func_num;
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/*
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* select to access the config space of func_no by setting func_no
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* to FUNC_SEL_SHIFT bit of PAB_CTRL register.
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*/
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func_num = csr_readl(pcie, PAB_CTRL);
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func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
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func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
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csr_writel(pcie, func_num, PAB_CTRL);
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}
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static void mobiveil_pcie_ep_func_deselect(struct mobiveil_pcie *pcie)
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{
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u32 func_num;
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/*
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* clear the FUNC_SEL_SHIFT bits when access other registers except
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* config space register.
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*/
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func_num = csr_readl(pcie, PAB_CTRL);
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func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
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csr_writel(pcie, func_num, PAB_CTRL);
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}
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static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
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{
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csr_writel(pcie, bar, GPEX_BAR_SELECT);
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csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
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csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
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}
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void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
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{
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__mobiveil_pcie_ep_reset_bar(pcie, bar);
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}
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static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
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u8 func_no, u8 cap_ptr, u8 cap)
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{
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u8 cap_id, next_cap_ptr;
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u16 reg;
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if (!cap_ptr)
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return 0;
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mobiveil_pcie_ep_func_select(pcie, func_no);
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reg = csr_readw(pcie, cap_ptr);
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cap_id = (reg & 0x00ff);
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mobiveil_pcie_ep_func_deselect(pcie);
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if (cap_id > PCI_CAP_ID_MAX)
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return 0;
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if (cap_id == cap)
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return cap_ptr;
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next_cap_ptr = (reg & 0xff00) >> 8;
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return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
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next_cap_ptr, cap);
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}
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static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie_ep *ep,
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u8 func_no, u8 cap)
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{
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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u8 next_cap_ptr;
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u16 reg;
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mobiveil_pcie_ep_func_select(pcie, func_no);
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reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
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next_cap_ptr = (reg & 0x00ff);
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mobiveil_pcie_ep_func_deselect(pcie);
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return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
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next_cap_ptr, cap);
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}
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static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
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struct pci_epf_header *hdr)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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mobiveil_pcie_ep_func_select(pcie, func_no);
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csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
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csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
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csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
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csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
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csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
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PCI_CLASS_DEVICE);
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csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
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csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
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csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
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csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
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mobiveil_pcie_ep_func_deselect(pcie);
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return 0;
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}
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static void mobiveil_pcie_ep_inbound_win(struct mobiveil_pcie_ep *ep,
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u8 func_no, enum pci_barno bar,
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dma_addr_t cpu_addr)
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{
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
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}
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static int mobiveil_pcie_ep_outbound_win(struct mobiveil_pcie_ep *ep,
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phys_addr_t phys_addr,
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u64 pci_addr, u8 func_no,
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size_t size)
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{
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u32 free_win;
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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free_win = find_first_zero_bit(ep->apio_wins_map, ep->apio_wins);
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if (free_win >= ep->apio_wins) {
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dev_err(&pcie->pdev->dev, "No free outbound window\n");
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return -EINVAL;
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}
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program_ob_windows_ep(pcie, func_no, free_win, phys_addr,
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pci_addr, MEM_WINDOW_TYPE, size);
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set_bit(free_win, ep->apio_wins_map);
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ep->apio_addr[free_win] = phys_addr;
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return 0;
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}
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static void mobiveil_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
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struct pci_epf_bar *epf_bar)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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enum pci_barno bar = epf_bar->barno;
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if (bar < ep->bar_num) {
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__mobiveil_pcie_ep_reset_bar(pcie, func_no * ep->bar_num + bar);
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mobiveil_pcie_disable_ib_win_ep(pcie, func_no, bar);
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}
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}
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static int mobiveil_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
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struct pci_epf_bar *epf_bar)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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enum pci_barno bar = epf_bar->barno;
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size_t size = epf_bar->size;
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if (bar < ep->bar_num) {
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mobiveil_pcie_ep_inbound_win(ep, func_no, bar,
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epf_bar->phys_addr);
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csr_writel(pcie, func_no * ep->bar_num + bar,
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GPEX_BAR_SELECT);
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csr_writel(pcie, lower_32_bits(~(size - 1)),
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GPEX_BAR_SIZE_LDW);
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csr_writel(pcie, upper_32_bits(~(size - 1)),
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GPEX_BAR_SIZE_UDW);
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}
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return 0;
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}
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static int mobiveil_pcie_find_index(struct mobiveil_pcie_ep *ep,
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phys_addr_t addr,
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u32 *atu_index)
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{
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u32 index;
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for (index = 0; index < ep->apio_wins; index++) {
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if (ep->apio_addr[index] != addr)
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continue;
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*atu_index = index;
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return 0;
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}
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return -EINVAL;
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}
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static void mobiveil_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
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phys_addr_t addr)
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{
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int ret;
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u32 atu_index;
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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ret = mobiveil_pcie_find_index(ep, addr, &atu_index);
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if (ret < 0)
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return;
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mobiveil_pcie_disable_ob_win(pcie, atu_index);
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clear_bit(atu_index, ep->apio_wins_map);
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}
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static int mobiveil_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
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phys_addr_t addr,
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u64 pci_addr, size_t size)
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{
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int ret;
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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ret = mobiveil_pcie_ep_outbound_win(ep, addr, pci_addr, func_no, size);
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if (ret) {
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dev_err(&pcie->pdev->dev, "Failed to enable address\n");
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return ret;
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}
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return 0;
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}
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static int mobiveil_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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u32 val, reg;
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u8 msi_cap;
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msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
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PCI_CAP_ID_MSI);
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if (!msi_cap)
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return -EINVAL;
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mobiveil_pcie_ep_func_select(pcie, func_no);
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reg = msi_cap + PCI_MSI_FLAGS;
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val = csr_readw(pcie, reg);
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mobiveil_pcie_ep_func_deselect(pcie);
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if (!(val & PCI_MSI_FLAGS_ENABLE))
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return -EINVAL;
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val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
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return val;
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}
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static int mobiveil_pcie_ep_set_msi(struct pci_epc *epc,
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u8 func_no, u8 interrupts)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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u32 val, reg;
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u8 msi_cap;
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msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
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PCI_CAP_ID_MSI);
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if (!msi_cap)
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return -EINVAL;
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mobiveil_pcie_ep_func_select(pcie, func_no);
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reg = msi_cap + PCI_MSI_FLAGS;
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val = csr_readw(pcie, reg);
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val &= ~PCI_MSI_FLAGS_QMASK;
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val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
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csr_writew(pcie, val, reg);
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mobiveil_pcie_ep_func_deselect(pcie);
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return 0;
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}
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static int mobiveil_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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u32 val, reg;
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u8 msix_cap;
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msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
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PCI_CAP_ID_MSIX);
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if (!msix_cap)
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return -EINVAL;
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mobiveil_pcie_ep_func_select(pcie, func_no);
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reg = msix_cap + PCI_MSIX_FLAGS;
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val = csr_readw(pcie, reg);
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mobiveil_pcie_ep_func_deselect(pcie);
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if (!(val & PCI_MSIX_FLAGS_ENABLE))
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return -EINVAL;
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val &= PCI_MSIX_FLAGS_QSIZE;
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return val;
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}
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static int mobiveil_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no,
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u16 interrupts)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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u32 val, reg;
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u8 msix_cap;
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msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
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PCI_CAP_ID_MSIX);
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if (!msix_cap)
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return -EINVAL;
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mobiveil_pcie_ep_func_select(pcie, func_no);
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reg = msix_cap + PCI_MSIX_FLAGS;
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val = csr_readw(pcie, reg);
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val &= ~PCI_MSIX_FLAGS_QSIZE;
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val |= interrupts;
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csr_writew(pcie, val, reg);
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mobiveil_pcie_ep_func_deselect(pcie);
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return 0;
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}
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static int mobiveil_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
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enum pci_epc_irq_type type,
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u16 interrupt_num)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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if (!ep->ops->raise_irq)
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return -EINVAL;
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return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
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}
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static const struct pci_epc_features*
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mobiveil_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
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{
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struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
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if (!ep->ops->get_features)
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return NULL;
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return ep->ops->get_features(ep);
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}
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static const struct pci_epc_ops epc_ops = {
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.write_header = mobiveil_pcie_ep_write_header,
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.set_bar = mobiveil_pcie_ep_set_bar,
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.clear_bar = mobiveil_pcie_ep_clear_bar,
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.map_addr = mobiveil_pcie_ep_map_addr,
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.unmap_addr = mobiveil_pcie_ep_unmap_addr,
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.set_msi = mobiveil_pcie_ep_set_msi,
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.get_msi = mobiveil_pcie_ep_get_msi,
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.set_msix = mobiveil_pcie_ep_set_msix,
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.get_msix = mobiveil_pcie_ep_get_msix,
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.raise_irq = mobiveil_pcie_ep_raise_irq,
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.get_features = mobiveil_pcie_ep_get_features,
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};
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int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no)
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{
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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dev_err(&pcie->pdev->dev, "EP cannot trigger legacy IRQs\n");
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return -EINVAL;
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}
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int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
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u8 interrupt_num)
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{
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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struct pci_epc *epc = ep->epc;
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u16 msg_ctrl, msg_data;
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u32 msg_addr_lower, msg_addr_upper, reg;
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u64 msg_addr;
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bool has_upper;
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int ret;
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u8 msi_cap;
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msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
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PCI_CAP_ID_MSI);
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if (!msi_cap)
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return -EINVAL;
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mobiveil_pcie_ep_func_select(pcie, func_no);
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reg = msi_cap + PCI_MSI_FLAGS;
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msg_ctrl = csr_readw(pcie, reg);
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has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
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reg = msi_cap + PCI_MSI_ADDRESS_LO;
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msg_addr_lower = csr_readl(pcie, reg);
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if (has_upper) {
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reg = msi_cap + PCI_MSI_ADDRESS_HI;
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msg_addr_upper = csr_readl(pcie, reg);
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reg = msi_cap + PCI_MSI_DATA_64;
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msg_data = csr_readw(pcie, reg);
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} else {
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msg_addr_upper = 0;
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reg = msi_cap + PCI_MSI_DATA_32;
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msg_data = csr_readw(pcie, reg);
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}
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msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
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mobiveil_pcie_ep_func_deselect(pcie);
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ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
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msg_addr, epc->mem->page_size);
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if (ret)
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return ret;
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writel(msg_data | (interrupt_num - 1), ep->msi_mem);
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mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
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return 0;
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}
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int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
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u16 interrupt_num)
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{
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struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
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struct pci_epc *epc = ep->epc;
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u32 msg_addr_upper, msg_addr_lower;
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u32 msg_data;
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u64 msg_addr;
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u8 msix_cap;
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int ret;
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msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
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PCI_CAP_ID_MSIX);
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if (!msix_cap)
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return -EINVAL;
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mobiveil_pcie_ep_func_deselect(pcie);
|
|
|
|
msg_addr_lower = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
|
|
PCI_MSIX_ENTRY_LOWER_ADDR +
|
|
(interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
|
|
msg_addr_upper = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
|
|
PCI_MSIX_ENTRY_UPPER_ADDR +
|
|
(interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
|
|
msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
|
|
msg_data = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
|
|
PCI_MSIX_ENTRY_DATA +
|
|
(interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
|
|
|
|
ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
|
|
msg_addr, epc->mem->page_size);
|
|
if (ret)
|
|
return ret;
|
|
|
|
writel(msg_data, ep->msi_mem);
|
|
|
|
mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mobiveil_pcie_ep_exit(struct mobiveil_pcie_ep *ep)
|
|
{
|
|
struct pci_epc *epc = ep->epc;
|
|
|
|
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
|
|
epc->mem->page_size);
|
|
|
|
pci_epc_mem_exit(epc);
|
|
}
|
|
|
|
int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep)
|
|
{
|
|
int ret;
|
|
void *addr;
|
|
struct pci_epc *epc;
|
|
struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
|
|
struct device *dev = &pcie->pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
|
|
if (!pcie->csr_axi_slave_base) {
|
|
dev_err(dev, "csr_base is not populated\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "apio-wins", &ep->apio_wins);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Unable to read apio-wins property\n");
|
|
return ret;
|
|
}
|
|
|
|
if (ep->apio_wins > MAX_IATU_OUT) {
|
|
dev_err(dev, "Invalid apio-wins\n");
|
|
return -EINVAL;
|
|
}
|
|
ep->apio_wins_map = devm_kcalloc(dev,
|
|
BITS_TO_LONGS(ep->apio_wins),
|
|
sizeof(long),
|
|
GFP_KERNEL);
|
|
if (!ep->apio_wins_map)
|
|
return -ENOMEM;
|
|
|
|
addr = devm_kcalloc(dev, ep->apio_wins, sizeof(phys_addr_t),
|
|
GFP_KERNEL);
|
|
if (!addr)
|
|
return -ENOMEM;
|
|
|
|
ep->apio_addr = addr;
|
|
|
|
mobiveil_pcie_enable_bridge_pio(pcie);
|
|
mobiveil_pcie_enable_engine_apio(pcie);
|
|
mobiveil_pcie_enable_engine_ppio(pcie);
|
|
mobiveil_pcie_enable_msi_ep(pcie);
|
|
|
|
epc = devm_pci_epc_create(dev, &epc_ops);
|
|
if (IS_ERR(epc)) {
|
|
dev_err(dev, "Failed to create epc device\n");
|
|
return PTR_ERR(epc);
|
|
}
|
|
|
|
ep->epc = epc;
|
|
epc_set_drvdata(epc, ep);
|
|
|
|
ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
|
|
if (ret < 0)
|
|
epc->max_functions = 1;
|
|
|
|
if (ep->ops->ep_init)
|
|
ep->ops->ep_init(ep);
|
|
|
|
ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
|
|
ep->page_size);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to initialize address space\n");
|
|
return ret;
|
|
}
|
|
|
|
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
|
|
epc->mem->page_size);
|
|
if (!ep->msi_mem) {
|
|
dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|