281 lines
5.6 KiB
Plaintext
281 lines
5.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/pads-imx8qm.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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model = "Freescale i.MX8QM MEK inmate";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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interrupt-parent = <&gic>;
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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aliases {
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mmc0 = &usdhc1;
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serial2 = &lpuart2;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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enable-method = "psci";
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reg = <0x0 0x2>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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enable-method = "psci";
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reg = <0x0 0x3>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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clock-frequency = <8333333>;
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};
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scu {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3",
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"gip3";
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mboxes = <&lsio_mu2 0 0
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&lsio_mu2 0 1
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&lsio_mu2 0 2
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&lsio_mu2 0 3
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&lsio_mu2 1 0
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&lsio_mu2 1 1
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&lsio_mu2 1 2
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&lsio_mu2 1 3
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&lsio_mu2 3 3>;
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pd: imx8qx-pd {
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compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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clk: clock-controller {
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compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
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#clock-cells = <2>;
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clocks = <&xtal32k &xtal24m>;
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clock-names = "xtal_32KHz", "xtal_24Mhz";
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};
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iomuxc: pinctrl {
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compatible = "fsl,imx8qm-iomuxc";
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};
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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clk_dummy: clock-dummy {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "clk_dummy";
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};
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xtal32k: clock-xtal32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xtal_32KHz";
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};
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xtal24m: clock-xtal24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xtal_24MHz";
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};
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pci@fd700000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
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<0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
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<0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
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<0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_EDGE_RISING>;
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reg = <0x0 0xfd700000 0x0 0x100000>;
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ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
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};
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/* For early console */
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serial@5a060000 {
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compatible = "fsl,imx8qm-lpuart";
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reg = <0x0 0x5a060000 0x0 0x1000>;
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};
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#include "imx8-ss-lsio.dtsi"
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#include "imx8-ss-adma.dtsi"
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#include "imx8-ss-conn.dtsi"
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};
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#include "imx8qm-ss-lsio.dtsi"
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#include "imx8qm-ss-dma.dtsi"
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#include "imx8qm-ss-conn.dtsi"
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&edma0 {
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status = "disabled";
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};
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&edma1 {
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status = "disabled";
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};
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&edma2 {
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status = "disabled";
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};
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&acm {
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status = "disabled";
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};
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&lsio_mu1 {
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status = "disabled";
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};
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&lsio_mu2 {
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status = "okay";
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};
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&lsio_gpio0 {
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status = "disabled";
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};
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&lsio_gpio1 {
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status = "disabled";
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};
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&lsio_gpio2 {
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status = "disabled";
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};
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&lsio_gpio3 {
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status = "disabled";
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};
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&lsio_gpio4 {
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status = "disabled";
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};
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&lsio_gpio5 {
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status = "disabled";
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};
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&lsio_gpio6 {
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status = "disabled";
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};
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&lsio_gpio7 {
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status = "disabled";
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};
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&fec1 {
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/delete-property/ iommus;
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};
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&fec2 {
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/delete-property/ iommus;
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};
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&usdhc1 {
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/delete-property/ iommus;
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};
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&usdhc2 {
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/delete-property/ iommus;
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};
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&usdhc3 {
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/delete-property/ iommus;
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};
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&usbotg3 {
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/delete-property/ iommus;
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};
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&iomuxc {
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pinctrl_lpuart2: lpuart2grp {
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fsl,pins = <
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IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
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IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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>;
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};
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};
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&lpuart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart2>;
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status = "okay";
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/delete-property/ dma-names;
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/delete-property/ dmas;
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1>;
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pinctrl-2 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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