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alistair23-linux/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017~2018 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8qxp.dtsi"
/ {
model = "Freescale i.MX8QXP LPDDR4 Validation Board";
compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp";
chosen {
stdout-path = &lpuart0;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
* Shouldn't be used at A core and Linux side.
*
*/
m4_reserved: m4@0x88000000 {
no-map;
reg = <0 0x88000000 0 0x8000000>;
};
rpmsg_reserved: rpmsg@0x90000000 {
no-map;
reg = <0 0x90000000 0 0x400000>;
};
rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0x90400000 0 0x100000>;
};
decoder_boot: decoder-boot@84000000 {
reg = <0 0x84000000 0 0x2000000>;
no-map;
};
encoder_boot: encoder-boot@86000000 {
reg = <0 0x86000000 0 0x200000>;
no-map;
};
decoder_rpc: decoder-rpc@0x92000000 {
reg = <0 0x92000000 0 0x200000>;
no-map;
};
encoder_rpc: encoder-rpc@0x92200000 {
reg = <0 0x92200000 0 0x200000>;
no-map;
};
encoder_reserved: encoder_reserved@94400000 {
no-map;
reg = <0 0x94400000 0 0x800000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
alloc-ranges = <0 0x96000000 0 0x3c000000>;
linux,cma-default;
};
};
reg_can_en: regulator-can-en {
compatible = "regulator-fixed";
regulator-name = "can-en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can_stby: regulator-can-stby {
compatible = "regulator-fixed";
regulator-name = "can-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_can_en>;
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator-usbotg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_audio: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound-cs42888 {
compatible = "fsl,imx8qm-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
esai-controller = <&esai0>;
audio-codec = <&cs42888>;
asrc-controller = <&asrc0>;
status = "okay";
};
};
&amix {
status = "okay";
};
&asrc0 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&asrc1 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&esai0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai0>;
assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&esai0_lpcg 0>;
assigned-clock-parents = <&aud_pll_div0_lpcg 0>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
status = "okay";
};
&sai4 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai4_lpcg 0>;
assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
fsl,sai-asynchronous;
fsl,txm-rxs;
status = "okay";
};
&sai5 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai5_lpcg 0>;
assigned-clock-parents = <&aud_pll_div1_lpcg 0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
fsl,sai-asynchronous;
fsl,txm-rxs;
status = "okay";
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-txid";
phy-handle = <&ethphy0>;
fsl,magic-packet;
nvmem-cells = <&fec_mac0>;
nvmem-cell-names = "mac-address";
fsl,rgmii_rxc_dly;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
at803x,vddio-1p8v;
status = "disabled";
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
&mlb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mlb>;
status = "disabled";
};
&usbphy1 {
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
disable-over-current;
status = "okay";
};
&usb3phynop1 {
status = "okay";
};
&usbotg3 {
dr_mode = "peripheral";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&thermal_zones {
pmic-thermal0 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 497>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&irqsteer_csi0 {
status = "okay";
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt35xu512aba@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-nor,ddr-quad-read-dummy = <8>;
};
};
&i2c_mipi_csi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
clock-frequency = <100000>;
status = "okay";
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&mclkout0_lpcg 0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg 0>;
assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>;
};
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
pca9557_a: gpio@18 {
compatible = "nxp,pca9557";
reg = <0x18>;
gpio-controller;
#gpio-cells = <2>;
};
pca9557_b: gpio@19 {
compatible = "nxp,pca9557";
reg = <0x19>;
gpio-controller;
#gpio-cells = <2>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 {
fsl,pins = <
IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020
IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020
>;
};
pinctrl_esai0: esai0grp {
fsl,pins = <
IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040
IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040
IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040
IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040
IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040
IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040
IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040
IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040
IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040
IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040
IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21
IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21
IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21
>;
};
pinctrl_flexcan3: flexcan3grp {
fsl,pins = <
IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21
IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
pinctrl_lpi2c3: lpi2cgrp {
fsl,pins = <
IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020
IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_mlb: mlbgrp {
fsl,pins = <
IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG 0x21
IMX8QXP_ESAI0_FST_CONN_MLB_CLK 0x21
IMX8QXP_ESAI0_TX0_CONN_MLB_DATA 0x21
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021
IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
};
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