![Venki Pallipadi](/assets/img/avatar_default.png)
Aviod TLB flush IPIs during C3 states by voluntary leave_mm() before entering C3. The performance impact of TLB flush on C3 should not be significant with respect to C3 wakeup latency. Also, CPUs tend to flush TLB in hardware while in C3 anyways. On a 8 logical CPU system, running make -j2, the number of tlbflush IPIs goes down from 40 per second to ~ 0. Total number of interrupts during the run of this workload was ~1200 per second, which makes it ~3% savings in wakeups. There was no measurable performance or power impact however. [ akpm@linux-foundation.org: symbol export fixes. ] Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
713 lines
17 KiB
C
713 lines
17 KiB
C
/*
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* Intel SMP support routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
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*
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* This code is released under the GNU General Public License version 2 or
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* later.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/cache.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <asm/mtrr.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <mach_apic.h>
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/*
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* Some notes on x86 processor bugs affecting SMP operation:
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*
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* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
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* The Linux implications for SMP are handled as follows:
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*
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* Pentium III / [Xeon]
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* None of the E1AP-E3AP errata are visible to the user.
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*
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* E1AP. see PII A1AP
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* E2AP. see PII A2AP
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* E3AP. see PII A3AP
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*
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* Pentium II / [Xeon]
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* None of the A1AP-A3AP errata are visible to the user.
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*
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* A1AP. see PPro 1AP
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* A2AP. see PPro 2AP
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* A3AP. see PPro 7AP
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*
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* Pentium Pro
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* None of 1AP-9AP errata are visible to the normal user,
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* except occasional delivery of 'spurious interrupt' as trap #15.
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* This is very rare and a non-problem.
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*
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* 1AP. Linux maps APIC as non-cacheable
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* 2AP. worked around in hardware
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* 3AP. fixed in C0 and above steppings microcode update.
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* Linux does not use excessive STARTUP_IPIs.
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* 4AP. worked around in hardware
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* 5AP. symmetric IO mode (normal Linux operation) not affected.
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* 'noapic' mode has vector 0xf filled out properly.
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* 6AP. 'noapic' mode might be affected - fixed in later steppings
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* 7AP. We do not assume writes to the LVT deassering IRQs
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* 8AP. We do not enable low power mode (deep sleep) during MP bootup
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* 9AP. We do not use mixed mode
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*
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* Pentium
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* There is a marginal case where REP MOVS on 100MHz SMP
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* machines with B stepping processors can fail. XXX should provide
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* an L1cache=Writethrough or L1cache=off option.
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*
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* B stepping CPUs may hang. There are hardware work arounds
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* for this. We warn about it in case your board doesn't have the work
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* arounds. Basically that's so I can tell anyone with a B stepping
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* CPU and SMP problems "tough".
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*
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* Specific items [From Pentium Processor Specification Update]
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*
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* 1AP. Linux doesn't use remote read
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* 2AP. Linux doesn't trust APIC errors
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* 3AP. We work around this
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* 4AP. Linux never generated 3 interrupts of the same priority
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* to cause a lost local interrupt.
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* 5AP. Remote read is never used
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* 6AP. not affected - worked around in hardware
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* 7AP. not affected - worked around in hardware
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* 8AP. worked around in hardware - we get explicit CS errors if not
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* 9AP. only 'noapic' mode affected. Might generate spurious
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* interrupts, we log only the first one and count the
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* rest silently.
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* 10AP. not affected - worked around in hardware
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* 11AP. Linux reads the APIC between writes to avoid this, as per
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* the documentation. Make sure you preserve this as it affects
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* the C stepping chips too.
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* 12AP. not affected - worked around in hardware
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* 13AP. not affected - worked around in hardware
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* 14AP. we always deassert INIT during bootup
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* 15AP. not affected - worked around in hardware
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* 16AP. not affected - worked around in hardware
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* 17AP. not affected - worked around in hardware
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* 18AP. not affected - worked around in hardware
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* 19AP. not affected - worked around in BIOS
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*
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* If this sounds worrying believe me these bugs are either ___RARE___,
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* or are signal timing bugs worked around in hardware and there's
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* about nothing of note with C stepping upwards.
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*/
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DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
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/*
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* the following functions deal with sending IPIs between CPUs.
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*
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* We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
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*/
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static inline int __prepare_ICR (unsigned int shortcut, int vector)
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{
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unsigned int icr = shortcut | APIC_DEST_LOGICAL;
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switch (vector) {
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default:
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icr |= APIC_DM_FIXED | vector;
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break;
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case NMI_VECTOR:
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icr |= APIC_DM_NMI;
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break;
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}
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return icr;
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}
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static inline int __prepare_ICR2 (unsigned int mask)
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{
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return SET_APIC_DEST_FIELD(mask);
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}
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void __send_IPI_shortcut(unsigned int shortcut, int vector)
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{
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/*
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* Subtle. In the case of the 'never do double writes' workaround
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* we have to lock out interrupts to be safe. As we don't care
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* of the value read we use an atomic rmw access to avoid costly
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* cli/sti. Otherwise we use an even cheaper single atomic write
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* to the APIC.
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*/
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unsigned int cfg;
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/*
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* Wait for idle.
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*/
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apic_wait_icr_idle();
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/*
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* No need to touch the target chip field
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*/
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cfg = __prepare_ICR(shortcut, vector);
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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apic_write_around(APIC_ICR, cfg);
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}
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void send_IPI_self(int vector)
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{
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__send_IPI_shortcut(APIC_DEST_SELF, vector);
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}
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/*
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* This is used to send an IPI with no shorthand notation (the destination is
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* specified in bits 56 to 63 of the ICR).
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*/
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static inline void __send_IPI_dest_field(unsigned long mask, int vector)
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{
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unsigned long cfg;
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/*
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* Wait for idle.
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*/
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if (unlikely(vector == NMI_VECTOR))
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safe_apic_wait_icr_idle();
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else
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apic_wait_icr_idle();
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/*
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* prepare target chip field
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*/
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cfg = __prepare_ICR2(mask);
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apic_write_around(APIC_ICR2, cfg);
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/*
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* program the ICR
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*/
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cfg = __prepare_ICR(0, vector);
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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apic_write_around(APIC_ICR, cfg);
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}
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/*
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* This is only used on smaller machines.
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*/
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void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
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{
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unsigned long mask = cpus_addr(cpumask)[0];
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unsigned long flags;
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local_irq_save(flags);
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WARN_ON(mask & ~cpus_addr(cpu_online_map)[0]);
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__send_IPI_dest_field(mask, vector);
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local_irq_restore(flags);
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}
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void send_IPI_mask_sequence(cpumask_t mask, int vector)
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{
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unsigned long flags;
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unsigned int query_cpu;
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/*
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* Hack. The clustered APIC addressing mode doesn't allow us to send
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* to an arbitrary mask, so I do a unicasts to each CPU instead. This
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* should be modified to do 1 message per cluster ID - mbligh
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*/
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local_irq_save(flags);
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for_each_possible_cpu(query_cpu) {
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if (cpu_isset(query_cpu, mask)) {
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__send_IPI_dest_field(cpu_to_logical_apicid(query_cpu),
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vector);
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}
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}
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local_irq_restore(flags);
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}
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#include <mach_ipi.h> /* must come after the send_IPI functions above for inlining */
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/*
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* Smarter SMP flushing macros.
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* c/o Linus Torvalds.
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*
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* These mean you can really definitely utterly forget about
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* writing to user space from interrupts. (Its not allowed anyway).
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*
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* Optimizations Manfred Spraul <manfred@colorfullife.com>
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*/
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static cpumask_t flush_cpumask;
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static struct mm_struct * flush_mm;
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static unsigned long flush_va;
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static DEFINE_SPINLOCK(tlbstate_lock);
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/*
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* We cannot call mmdrop() because we are in interrupt context,
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* instead update mm->cpu_vm_mask.
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*
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* We need to reload %cr3 since the page tables may be going
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* away from under us..
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*/
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void leave_mm(int cpu)
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{
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if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
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BUG();
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cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
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load_cr3(swapper_pg_dir);
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}
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EXPORT_SYMBOL_GPL(leave_mm);
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/*
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*
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* The flush IPI assumes that a thread switch happens in this order:
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* [cpu0: the cpu that switches]
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* 1) switch_mm() either 1a) or 1b)
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* 1a) thread switch to a different mm
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* 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
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* Stop ipi delivery for the old mm. This is not synchronized with
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* the other cpus, but smp_invalidate_interrupt ignore flush ipis
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* for the wrong mm, and in the worst case we perform a superfluous
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* tlb flush.
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* 1a2) set cpu_tlbstate to TLBSTATE_OK
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* Now the smp_invalidate_interrupt won't call leave_mm if cpu0
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* was in lazy tlb mode.
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* 1a3) update cpu_tlbstate[].active_mm
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* Now cpu0 accepts tlb flushes for the new mm.
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* 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
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* Now the other cpus will send tlb flush ipis.
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* 1a4) change cr3.
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* 1b) thread switch without mm change
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* cpu_tlbstate[].active_mm is correct, cpu0 already handles
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* flush ipis.
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* 1b1) set cpu_tlbstate to TLBSTATE_OK
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* 1b2) test_and_set the cpu bit in cpu_vm_mask.
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* Atomically set the bit [other cpus will start sending flush ipis],
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* and test the bit.
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* 1b3) if the bit was 0: leave_mm was called, flush the tlb.
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* 2) switch %%esp, ie current
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*
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* The interrupt must handle 2 special cases:
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* - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
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* - the cpu performs speculative tlb reads, i.e. even if the cpu only
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* runs in kernel space, the cpu could load tlb entries for user space
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* pages.
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*
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* The good news is that cpu_tlbstate is local to each cpu, no
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* write/read ordering problems.
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*/
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/*
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* TLB flush IPI:
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*
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* 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
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* 2) Leave the mm if we are in the lazy tlb mode.
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*/
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void smp_invalidate_interrupt(struct pt_regs *regs)
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{
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unsigned long cpu;
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cpu = get_cpu();
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if (!cpu_isset(cpu, flush_cpumask))
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goto out;
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/*
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* This was a BUG() but until someone can quote me the
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* line from the intel manual that guarantees an IPI to
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* multiple CPUs is retried _only_ on the erroring CPUs
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* its staying as a return
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*
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* BUG();
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*/
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if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
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if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
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if (flush_va == TLB_FLUSH_ALL)
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local_flush_tlb();
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else
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__flush_tlb_one(flush_va);
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} else
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leave_mm(cpu);
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}
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ack_APIC_irq();
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smp_mb__before_clear_bit();
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cpu_clear(cpu, flush_cpumask);
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smp_mb__after_clear_bit();
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out:
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put_cpu_no_resched();
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__get_cpu_var(irq_stat).irq_tlb_count++;
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}
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void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm,
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unsigned long va)
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{
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cpumask_t cpumask = *cpumaskp;
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/*
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* A couple of (to be removed) sanity checks:
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*
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* - current CPU must not be in mask
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* - mask must exist :)
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*/
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BUG_ON(cpus_empty(cpumask));
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BUG_ON(cpu_isset(smp_processor_id(), cpumask));
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BUG_ON(!mm);
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#ifdef CONFIG_HOTPLUG_CPU
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/* If a CPU which we ran on has gone down, OK. */
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cpus_and(cpumask, cpumask, cpu_online_map);
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if (unlikely(cpus_empty(cpumask)))
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return;
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#endif
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/*
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* i'm not happy about this global shared spinlock in the
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* MM hot path, but we'll see how contended it is.
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* AK: x86-64 has a faster method that could be ported.
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*/
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spin_lock(&tlbstate_lock);
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flush_mm = mm;
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flush_va = va;
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cpus_or(flush_cpumask, cpumask, flush_cpumask);
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/*
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* We have to send the IPI only to
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* CPUs affected.
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*/
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send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
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while (!cpus_empty(flush_cpumask))
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/* nothing. lockup detection does not belong here */
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cpu_relax();
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flush_mm = NULL;
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flush_va = 0;
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spin_unlock(&tlbstate_lock);
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}
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void flush_tlb_current_task(void)
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{
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struct mm_struct *mm = current->mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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local_flush_tlb();
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_mm (struct mm_struct * mm)
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{
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if (current->mm)
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local_flush_tlb();
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
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{
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struct mm_struct *mm = vma->vm_mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if(current->mm)
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__flush_tlb_one(va);
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, va);
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preempt_enable();
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}
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EXPORT_SYMBOL(flush_tlb_page);
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static void do_flush_tlb_all(void* info)
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{
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unsigned long cpu = smp_processor_id();
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__flush_tlb_all();
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if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
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leave_mm(cpu);
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
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}
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/*
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* this function sends a 'reschedule' IPI to another CPU.
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* it goes straight through and wastes no time serializing
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* anything. Worst case is that we lose a reschedule ...
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*/
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static void native_smp_send_reschedule(int cpu)
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{
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WARN_ON(cpu_is_offline(cpu));
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send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
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}
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/*
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* Structure and data for smp_call_function(). This is designed to minimise
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* static memory requirements. It also looks cleaner.
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*/
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static DEFINE_SPINLOCK(call_lock);
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struct call_data_struct {
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void (*func) (void *info);
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void *info;
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atomic_t started;
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atomic_t finished;
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int wait;
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};
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void lock_ipi_call_lock(void)
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{
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spin_lock_irq(&call_lock);
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}
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void unlock_ipi_call_lock(void)
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{
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spin_unlock_irq(&call_lock);
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}
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static struct call_data_struct *call_data;
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static void __smp_call_function(void (*func) (void *info), void *info,
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int nonatomic, int wait)
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{
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struct call_data_struct data;
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int cpus = num_online_cpus() - 1;
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if (!cpus)
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return;
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data.func = func;
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data.info = info;
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atomic_set(&data.started, 0);
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data.wait = wait;
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if (wait)
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atomic_set(&data.finished, 0);
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call_data = &data;
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mb();
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/* Send a message to all other CPUs and wait for them to respond */
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send_IPI_allbutself(CALL_FUNCTION_VECTOR);
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/* Wait for response */
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while (atomic_read(&data.started) != cpus)
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cpu_relax();
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if (wait)
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while (atomic_read(&data.finished) != cpus)
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cpu_relax();
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}
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|
|
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/**
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* smp_call_function_mask(): Run a function on a set of other CPUs.
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* @mask: The set of cpus to run on. Must not include the current cpu.
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* @func: The function to run. This must be fast and non-blocking.
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* @info: An arbitrary pointer to pass to the function.
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* @wait: If true, wait (atomically) until function has completed on other CPUs.
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*
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* Returns 0 on success, else a negative status code.
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*
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* If @wait is true, then returns once @func has returned; otherwise
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* it returns just before the target cpu calls @func.
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*
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* You must not call this function with disabled interrupts or from a
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* hardware interrupt handler or from a bottom half handler.
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*/
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static int
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native_smp_call_function_mask(cpumask_t mask,
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void (*func)(void *), void *info,
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|
int wait)
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|
{
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struct call_data_struct data;
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|
cpumask_t allbutself;
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|
int cpus;
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|
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/* Can deadlock when called with interrupts disabled */
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WARN_ON(irqs_disabled());
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|
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/* Holding any lock stops cpus from going down. */
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spin_lock(&call_lock);
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allbutself = cpu_online_map;
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cpu_clear(smp_processor_id(), allbutself);
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cpus_and(mask, mask, allbutself);
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cpus = cpus_weight(mask);
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|
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if (!cpus) {
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spin_unlock(&call_lock);
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return 0;
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}
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|
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|
data.func = func;
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data.info = info;
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atomic_set(&data.started, 0);
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data.wait = wait;
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if (wait)
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atomic_set(&data.finished, 0);
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|
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call_data = &data;
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mb();
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|
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/* Send a message to other CPUs */
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|
if (cpus_equal(mask, allbutself))
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|
send_IPI_allbutself(CALL_FUNCTION_VECTOR);
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else
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|
send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
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|
|
|
/* Wait for response */
|
|
while (atomic_read(&data.started) != cpus)
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|
cpu_relax();
|
|
|
|
if (wait)
|
|
while (atomic_read(&data.finished) != cpus)
|
|
cpu_relax();
|
|
spin_unlock(&call_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void stop_this_cpu (void * dummy)
|
|
{
|
|
local_irq_disable();
|
|
/*
|
|
* Remove this CPU:
|
|
*/
|
|
cpu_clear(smp_processor_id(), cpu_online_map);
|
|
disable_local_APIC();
|
|
if (cpu_data(smp_processor_id()).hlt_works_ok)
|
|
for(;;) halt();
|
|
for (;;);
|
|
}
|
|
|
|
/*
|
|
* this function calls the 'stop' function on all other CPUs in the system.
|
|
*/
|
|
|
|
static void native_smp_send_stop(void)
|
|
{
|
|
/* Don't deadlock on the call lock in panic */
|
|
int nolock = !spin_trylock(&call_lock);
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
__smp_call_function(stop_this_cpu, NULL, 0, 0);
|
|
if (!nolock)
|
|
spin_unlock(&call_lock);
|
|
disable_local_APIC();
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/*
|
|
* Reschedule call back. Nothing to do,
|
|
* all the work is done automatically when
|
|
* we return from the interrupt.
|
|
*/
|
|
void smp_reschedule_interrupt(struct pt_regs *regs)
|
|
{
|
|
ack_APIC_irq();
|
|
__get_cpu_var(irq_stat).irq_resched_count++;
|
|
}
|
|
|
|
void smp_call_function_interrupt(struct pt_regs *regs)
|
|
{
|
|
void (*func) (void *info) = call_data->func;
|
|
void *info = call_data->info;
|
|
int wait = call_data->wait;
|
|
|
|
ack_APIC_irq();
|
|
/*
|
|
* Notify initiating CPU that I've grabbed the data and am
|
|
* about to execute the function
|
|
*/
|
|
mb();
|
|
atomic_inc(&call_data->started);
|
|
/*
|
|
* At this point the info structure may be out of scope unless wait==1
|
|
*/
|
|
irq_enter();
|
|
(*func)(info);
|
|
__get_cpu_var(irq_stat).irq_call_count++;
|
|
irq_exit();
|
|
|
|
if (wait) {
|
|
mb();
|
|
atomic_inc(&call_data->finished);
|
|
}
|
|
}
|
|
|
|
static int convert_apicid_to_cpu(int apic_id)
|
|
{
|
|
int i;
|
|
|
|
for_each_possible_cpu(i) {
|
|
if (per_cpu(x86_cpu_to_apicid, i) == apic_id)
|
|
return i;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
int safe_smp_processor_id(void)
|
|
{
|
|
int apicid, cpuid;
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_APIC))
|
|
return 0;
|
|
|
|
apicid = hard_smp_processor_id();
|
|
if (apicid == BAD_APICID)
|
|
return 0;
|
|
|
|
cpuid = convert_apicid_to_cpu(apicid);
|
|
|
|
return cpuid >= 0 ? cpuid : 0;
|
|
}
|
|
|
|
struct smp_ops smp_ops = {
|
|
.smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
|
|
.smp_prepare_cpus = native_smp_prepare_cpus,
|
|
.cpu_up = native_cpu_up,
|
|
.smp_cpus_done = native_smp_cpus_done,
|
|
|
|
.smp_send_stop = native_smp_send_stop,
|
|
.smp_send_reschedule = native_smp_send_reschedule,
|
|
.smp_call_function_mask = native_smp_call_function_mask,
|
|
};
|
|
EXPORT_SYMBOL_GPL(smp_ops);
|