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alistair23-linux/arch/arm64/boot/dts/freescale/imx8mq-evk.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017 NXP
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mq.dtsi"
/ {
model = "NXP i.MX8MQ EVK";
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0xc0000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg_reserved: rpmsg@0xb8000000 {
no-map;
reg = <0 0xb8000000 0 0x400000>;
};
};
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
reset-post-delay-ms = <40>;
#reset-cells = <0>;
};
resmem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
alloc-ranges = <0 0x40000000 0 0x40000000>;
linux,cma-default;
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
ptn36043 {
compatible = "nxp,ptn36043";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ss_sel>;
switch-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
orientation-switch;
port {
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
buck2_reg: regulator-buck2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_buck2>;
compatible = "regulator-gpio";
regulator-name = "vdd_arm";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
states = <1000000 0x0
900000 0x1>;
};
bt_sco_codec: bt_sco_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai3>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco_codec 1>;
};
};
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&cpudai>;
simple-audio-card,bitclock-master = <&cpudai>;
simple-audio-card,widgets =
"Line", "Left Line Out Jack",
"Line", "Right Line Out Jack";
simple-audio-card,routing =
"Left Line Out Jack", "LINEVOUTL",
"Right Line Out Jack", "LINEVOUTR";
cpudai: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
};
link_codec: simple-audio-card,codec {
sound-dai = <&wm8524>;
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
};
};
sound-hdmi {
compatible = "fsl,imx8mq-evk-cdnhdmi",
"fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi";
audio-cpu = <&sai4>;
protocol = <1>;
hdmi-out;
constraint-rate = <44100>,
<88200>,
<176400>,
<32000>,
<48000>,
<96000>,
<192000>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
sound-hdmi-arc {
compatible = "fsl,imx-audio-spdif";
model = "imx-hdmi-arc";
spdif-controller = <&spdif2>;
spdif-in;
};
sound-ak4458 {
compatible = "fsl,imx-audio-ak4458-mq";
model = "ak4458-audio";
audio-cpu = <&sai1>;
audio-codec = <&ak4458_1>, <&ak4458_2>;
ak4458,pdn-gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>;
};
sound-ak5558 {
compatible = "fsl,imx-audio-ak5558-mq";
model = "ak5558-audio";
audio-cpu = <&sai5>;
audio-codec = <&ak5558>;
};
sound-ak4497 {
compatible = "fsl,imx-audio-ak4497-mq";
model = "ak4497-audio";
audio-cpu = <&sai1>;
audio-codec = <&ak4497>;
status = "disabled";
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&csi1_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};
&csi2_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi2_ep: endpoint {
remote-endpoint = <&csi2_mipi_ep>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
};
};
};
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi1_sensor_ep: endpoint@0 {
remote-endpoint = <&ov5640_mipi1_ep>;
data-lanes = <1 2>;
bus-type = <4>;
};
csi1_mipi_ep: endpoint@1 {
remote-endpoint = <&csi1_ep>;
};
};
};
&mipi_csi_2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi2_sensor_ep: endpoint@0 {
remote-endpoint = <&ov5640_mipi2_ep>;
data-lanes = <1 2>;
bus-type = <4>;
};
csi2_mipi_ep: endpoint@1 {
remote-endpoint = <&csi2_ep>;
};
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai1 {
pinctrl-names = "default", "pcm_b2m", "dsd";
pinctrl-0 = <&pinctrl_sai1_pcm>;
pinctrl-1 = <&pinctrl_sai1_pcm_b2m>;
pinctrl-2 = <&pinctrl_sai1_dsd>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
fsl,sai-multi-lane;
fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>;
dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>;
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai4 {
assigned-clocks = <&clk IMX8MQ_CLK_SAI4>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
fsl,sai-asynchronous;
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_CLK_SPDIF1>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_AUDIO_PLL1_OUT>, <&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
"rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
status = "okay";
};
&spdif2 {
assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reset>;
wl-reg-on {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
ov5640_mipi2: ov5640_mipi2@3c {
compatible = "ovti,ov5640_mipi";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <20000000>;
csi_id = <1>;
pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
mclk = <20000000>;
mclk_source = <0>;
port {
ov5640_mipi2_ep: endpoint {
remote-endpoint = <&mipi2_sensor_ep>;
};
};
};
pmic@8 {
compatible = "fsl,pfuze100";
fsl,pfuze-support-disable-sw;
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <3 8>;
port {
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
synaptics_dsx_ts: synaptics_dsx_ts@20 {
compatible = "synaptics_dsx";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
synaptics,diagonal-rotation;
status = "disabled";
};
ak4458_1: ak4458@10 {
compatible = "asahi-kasei,ak4458";
reg = <0x10>;
};
ak4458_2: ak4458@12 {
compatible = "asahi-kasei,ak4458";
reg = <0x12>;
};
ak5558: ak5558@13 {
compatible = "asahi-kasei,ak5558";
reg = <0x13>;
ak5558,pdn-gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>;
};
ak4497: ak4497@11 {
compatible = "asahi-kasei,ak4497";
reg = <0x11>;
ak4497,pdn-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};
adv_bridge: adv7535@3d {
compatible = "adi,adv7535";
reg = <0x3d>;
adi,addr-cec = <0x3b>;
adi,dsi-lanes = <4>;
pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov5640_mipi: ov5640_mipi@3c {
compatible = "ovti,ov5640_mipi";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1_pwn>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <20000000>;
csi_id = <0>;
pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
mclk = <20000000>;
mclk_source = <0>;
port {
ov5640_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
hard-wired = <1>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
reserved-region = <&rpmsg_reserved>;
status = "okay";
};
&pcie1_ep {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "disabled";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&snvs_pwrkey {
status = "okay";
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash0: n25q256a@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-nor,ddr-quad-read-dummy = <6>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart3 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
fsl,uart-has-rtscts;
resets = <&modem_reset>;
status = "okay";
};
&usb3_phy0 {
vbus-power-supply = <&ptn5110>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x16
>;
};
pinctrl_buck2: vddarmgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
>;
};
pinctrl_csi1_pwn: csi1_pwn_grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
>;
};
pinctrl_csi2_pwn: csi2_pwn_grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
>;
};
pinctrl_csi_rst: csi_rst_grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c1_dsi_ts_int: dsi_ts_int {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */
MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_sai1_pcm: sai1grp_pcm {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai1_dsd: sai1grp_dsd {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6
MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6
MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_ss_sel: usb3ssgrp{
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdog1grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_wifi_reset: wifiresetgrp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
>;
};
};
&vpu {
status = "okay";
};
&gpu3d {
status = "okay";
};
&irqsteer {
status = "okay";
};
&dcss {
status = "okay";
port@0 {
dcss_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
&hdmi {
compatible = "cdn,imx8mq-hdmi";
lane-mapping = <0xe4>;
status = "okay";
port@1 {
hdmi_in: endpoint {
remote-endpoint = <&dcss_out>;
};
};
};
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