![Tony Lindgren](/assets/img/avatar_default.png)
This patch syncs omap specific core code with linux-omap. Most of the changes are needed to fix bitrot caused by driver updates in linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
529 lines
13 KiB
C
529 lines
13 KiB
C
/*
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* linux/arch/arm/plat-omap/dmtimer.c
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*
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* OMAP Dual-Mode Timers
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*
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* Copyright (C) 2005 Nokia Corporation
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* OMAP2 support by Juha Yrjola
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* API improvements and OMAP2 clock framework support by Timo Teras
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <asm/hardware.h>
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#include <asm/arch/dmtimer.h>
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#include <asm/io.h>
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#include <asm/arch/irqs.h>
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/* register offsets */
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#define OMAP_TIMER_ID_REG 0x00
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#define OMAP_TIMER_OCP_CFG_REG 0x10
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#define OMAP_TIMER_SYS_STAT_REG 0x14
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#define OMAP_TIMER_STAT_REG 0x18
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#define OMAP_TIMER_INT_EN_REG 0x1c
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#define OMAP_TIMER_WAKEUP_EN_REG 0x20
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#define OMAP_TIMER_CTRL_REG 0x24
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#define OMAP_TIMER_COUNTER_REG 0x28
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#define OMAP_TIMER_LOAD_REG 0x2c
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#define OMAP_TIMER_TRIGGER_REG 0x30
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#define OMAP_TIMER_WRITE_PEND_REG 0x34
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#define OMAP_TIMER_MATCH_REG 0x38
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#define OMAP_TIMER_CAPTURE_REG 0x3c
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#define OMAP_TIMER_IF_CTRL_REG 0x40
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/* timer control reg bits */
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#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
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#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
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#define OMAP_TIMER_CTRL_PT (1 << 12)
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#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
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#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
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#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
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#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
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#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
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#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
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#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
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#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
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#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
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struct omap_dm_timer {
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unsigned long phys_base;
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int irq;
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#ifdef CONFIG_ARCH_OMAP2
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struct clk *iclk, *fclk;
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#endif
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void __iomem *io_base;
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unsigned reserved:1;
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unsigned enabled:1;
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};
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#ifdef CONFIG_ARCH_OMAP1
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#define omap_dm_clk_enable(x)
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#define omap_dm_clk_disable(x)
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static struct omap_dm_timer dm_timers[] = {
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{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
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{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
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{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
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{ .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
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{ .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
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{ .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
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{ .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
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{ .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
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};
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#elif defined(CONFIG_ARCH_OMAP2)
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#define omap_dm_clk_enable(x) clk_enable(x)
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#define omap_dm_clk_disable(x) clk_disable(x)
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static struct omap_dm_timer dm_timers[] = {
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{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
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{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
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{ .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
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{ .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
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{ .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
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{ .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
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{ .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
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{ .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
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{ .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
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{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
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{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
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{ .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
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};
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static const char *dm_source_names[] = {
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"sys_ck",
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"func_32k_ck",
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"alt_ck"
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};
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static struct clk *dm_source_clocks[3];
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#else
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#error OMAP architecture not supported!
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#endif
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static const int dm_timer_count = ARRAY_SIZE(dm_timers);
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static spinlock_t dm_timer_lock;
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
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{
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return readl(timer->io_base + reg);
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}
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static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
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{
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writel(value, timer->io_base + reg);
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while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
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;
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}
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static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
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{
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int c;
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c = 0;
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while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
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c++;
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if (c > 100000) {
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printk(KERN_ERR "Timer failed to reset\n");
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return;
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}
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}
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}
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static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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{
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u32 l;
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if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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omap_dm_timer_wait_for_reset(timer);
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}
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omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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/* Set to smart-idle mode */
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
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l |= 0x02 << 3;
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if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
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/* Enable wake-up only for GPT1 on OMAP2 CPUs*/
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l |= 1 << 2;
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/* Non-posted mode */
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
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}
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omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
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}
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static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
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{
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omap_dm_timer_enable(timer);
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omap_dm_timer_reset(timer);
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}
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struct omap_dm_timer *omap_dm_timer_request(void)
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{
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struct omap_dm_timer *timer = NULL;
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unsigned long flags;
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int i;
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spin_lock_irqsave(&dm_timer_lock, flags);
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for (i = 0; i < dm_timer_count; i++) {
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if (dm_timers[i].reserved)
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continue;
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timer = &dm_timers[i];
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timer->reserved = 1;
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break;
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}
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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if (timer != NULL)
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omap_dm_timer_prepare(timer);
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return timer;
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}
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struct omap_dm_timer *omap_dm_timer_request_specific(int id)
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{
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struct omap_dm_timer *timer;
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unsigned long flags;
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spin_lock_irqsave(&dm_timer_lock, flags);
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if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
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__FILE__, __LINE__, __FUNCTION__, id);
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dump_stack();
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return NULL;
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}
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timer = &dm_timers[id-1];
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timer->reserved = 1;
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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omap_dm_timer_prepare(timer);
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return timer;
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}
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void omap_dm_timer_free(struct omap_dm_timer *timer)
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{
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omap_dm_timer_enable(timer);
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omap_dm_timer_reset(timer);
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omap_dm_timer_disable(timer);
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WARN_ON(!timer->reserved);
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timer->reserved = 0;
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}
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void omap_dm_timer_enable(struct omap_dm_timer *timer)
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{
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if (timer->enabled)
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return;
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omap_dm_clk_enable(timer->fclk);
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omap_dm_clk_enable(timer->iclk);
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timer->enabled = 1;
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}
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void omap_dm_timer_disable(struct omap_dm_timer *timer)
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{
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if (!timer->enabled)
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return;
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omap_dm_clk_disable(timer->iclk);
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omap_dm_clk_disable(timer->fclk);
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timer->enabled = 0;
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}
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
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{
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return timer->irq;
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}
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#if defined(CONFIG_ARCH_OMAP1)
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struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
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{
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BUG();
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}
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/**
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* omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
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* @inputmask: current value of idlect mask
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*/
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
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{
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int i;
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/* If ARMXOR cannot be idled this function call is unnecessary */
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if (!(inputmask & (1 << 1)))
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return inputmask;
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/* If any active timer is using ARMXOR return modified mask */
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for (i = 0; i < dm_timer_count; i++) {
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u32 l;
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l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
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if (l & OMAP_TIMER_CTRL_ST) {
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if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
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inputmask &= ~(1 << 1);
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else
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inputmask &= ~(1 << 2);
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}
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}
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return inputmask;
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}
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#elif defined(CONFIG_ARCH_OMAP2)
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struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
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{
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return timer->fclk;
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}
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
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{
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BUG();
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return 0;
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}
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#endif
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void omap_dm_timer_trigger(struct omap_dm_timer *timer)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
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}
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void omap_dm_timer_start(struct omap_dm_timer *timer)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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if (!(l & OMAP_TIMER_CTRL_ST)) {
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l |= OMAP_TIMER_CTRL_ST;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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}
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void omap_dm_timer_stop(struct omap_dm_timer *timer)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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if (l & OMAP_TIMER_CTRL_ST) {
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l &= ~0x1;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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}
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#ifdef CONFIG_ARCH_OMAP1
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void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
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{
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int n = (timer - dm_timers) << 1;
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u32 l;
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l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
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l |= source << n;
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omap_writel(l, MOD_CONF_CTRL_1);
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}
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#else
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void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
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{
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if (source < 0 || source >= 3)
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return;
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clk_disable(timer->fclk);
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clk_set_parent(timer->fclk, dm_source_clocks[source]);
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clk_enable(timer->fclk);
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/* When the functional clock disappears, too quick writes seem to
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* cause an abort. */
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__delay(150000);
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}
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#endif
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void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
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unsigned int load)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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if (autoreload)
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l |= OMAP_TIMER_CTRL_AR;
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else
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l &= ~OMAP_TIMER_CTRL_AR;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
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}
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void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
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unsigned int match)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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if (enable)
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l |= OMAP_TIMER_CTRL_CE;
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else
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l &= ~OMAP_TIMER_CTRL_CE;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
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}
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void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
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int toggle, int trigger)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
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OMAP_TIMER_CTRL_PT | (0x03 << 10));
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if (def_on)
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l |= OMAP_TIMER_CTRL_SCPWM;
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if (toggle)
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l |= OMAP_TIMER_CTRL_PT;
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l |= trigger << 10;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
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{
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
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if (prescaler >= 0x00 && prescaler <= 0x07) {
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l |= OMAP_TIMER_CTRL_PRE;
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l |= prescaler << 2;
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}
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
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unsigned int value)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
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}
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unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
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{
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unsigned int l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
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return l;
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}
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void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
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}
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unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
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{
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unsigned int l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
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return l;
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}
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void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
|
|
}
|
|
|
|
int omap_dm_timers_active(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < dm_timer_count; i++) {
|
|
struct omap_dm_timer *timer;
|
|
|
|
timer = &dm_timers[i];
|
|
|
|
if (!timer->enabled)
|
|
continue;
|
|
|
|
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
|
|
OMAP_TIMER_CTRL_ST) {
|
|
return 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int omap_dm_timer_init(void)
|
|
{
|
|
struct omap_dm_timer *timer;
|
|
int i;
|
|
|
|
if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
|
|
return -ENODEV;
|
|
|
|
spin_lock_init(&dm_timer_lock);
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
|
|
dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
|
|
BUG_ON(dm_source_clocks[i] == NULL);
|
|
}
|
|
#endif
|
|
if (cpu_is_omap243x())
|
|
dm_timers[0].phys_base = 0x49018000;
|
|
|
|
for (i = 0; i < dm_timer_count; i++) {
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
char clk_name[16];
|
|
#endif
|
|
|
|
timer = &dm_timers[i];
|
|
timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
sprintf(clk_name, "gpt%d_ick", i + 1);
|
|
timer->iclk = clk_get(NULL, clk_name);
|
|
sprintf(clk_name, "gpt%d_fck", i + 1);
|
|
timer->fclk = clk_get(NULL, clk_name);
|
|
#endif
|
|
}
|
|
|
|
return 0;
|
|
}
|