7f646e9276
This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using the generic IRQ chip driver with separate enable and disable registers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lkml.kernel.org/r/1400892054-24457-2-git-send-email-f.fainelli@gmail.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
94 lines
1.5 KiB
Plaintext
94 lines
1.5 KiB
Plaintext
config IRQCHIP
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def_bool y
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depends on OF_IRQ
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config ARM_GIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config GIC_NON_BANKED
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bool
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 3 if ARCH_S5PC100
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config BRCMSTB_L2_IRQ
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bool
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depends on ARM
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DW_APB_ICTL
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bool
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select IRQ_DOMAIN
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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default y
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
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config RENESAS_IRQC
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bool
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select IRQ_DOMAIN
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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config IRQ_CROSSBAR
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bool
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help
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Support for a CROSSBAR ip that preceeds the main interrupt controller.
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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