![Christian König](/assets/img/avatar_default.png)
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
879 lines
22 KiB
C
879 lines
22 KiB
C
/*
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* Copyright 2008 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include <linux/list_sort.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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#define AMDGPU_CS_MAX_PRIORITY 32u
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#define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1)
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/* This is based on the bucket sort with O(n) time complexity.
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* An item with priority "i" is added to bucket[i]. The lists are then
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* concatenated in descending order.
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*/
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struct amdgpu_cs_buckets {
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struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
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};
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static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
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{
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unsigned i;
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for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
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INIT_LIST_HEAD(&b->bucket[i]);
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}
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static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
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struct list_head *item, unsigned priority)
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{
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/* Since buffers which appear sooner in the relocation list are
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* likely to be used more often than buffers which appear later
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* in the list, the sort mustn't change the ordering of buffers
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* with the same priority, i.e. it must be stable.
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*/
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list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
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}
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static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
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struct list_head *out_list)
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{
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unsigned i;
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/* Connect the sorted buckets in the output list. */
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for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
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list_splice(&b->bucket[i], out_list);
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}
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}
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int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
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u32 ip_instance, u32 ring,
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struct amdgpu_ring **out_ring)
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{
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/* Right now all IPs have only one instance - multiple rings. */
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if (ip_instance != 0) {
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DRM_ERROR("invalid ip instance: %d\n", ip_instance);
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return -EINVAL;
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}
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switch (ip_type) {
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default:
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DRM_ERROR("unknown ip type: %d\n", ip_type);
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return -EINVAL;
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case AMDGPU_HW_IP_GFX:
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if (ring < adev->gfx.num_gfx_rings) {
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*out_ring = &adev->gfx.gfx_ring[ring];
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} else {
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DRM_ERROR("only %d gfx rings are supported now\n",
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adev->gfx.num_gfx_rings);
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return -EINVAL;
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}
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break;
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case AMDGPU_HW_IP_COMPUTE:
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if (ring < adev->gfx.num_compute_rings) {
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*out_ring = &adev->gfx.compute_ring[ring];
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} else {
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DRM_ERROR("only %d compute rings are supported now\n",
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adev->gfx.num_compute_rings);
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return -EINVAL;
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}
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break;
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case AMDGPU_HW_IP_DMA:
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if (ring < 2) {
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*out_ring = &adev->sdma[ring].ring;
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} else {
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DRM_ERROR("only two SDMA rings are supported\n");
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return -EINVAL;
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}
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break;
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case AMDGPU_HW_IP_UVD:
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*out_ring = &adev->uvd.ring;
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break;
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case AMDGPU_HW_IP_VCE:
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if (ring < 2){
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*out_ring = &adev->vce.ring[ring];
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} else {
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DRM_ERROR("only two VCE rings are supported\n");
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return -EINVAL;
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}
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break;
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}
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return 0;
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}
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int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
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{
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union drm_amdgpu_cs *cs = data;
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uint64_t *chunk_array_user;
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uint64_t *chunk_array = NULL;
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struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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unsigned size, i;
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int r = 0;
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if (!cs->in.num_chunks)
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goto out;
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p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
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if (!p->ctx) {
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r = -EINVAL;
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goto out;
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}
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p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
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/* get chunks */
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INIT_LIST_HEAD(&p->validated);
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chunk_array = kcalloc(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
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if (chunk_array == NULL) {
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r = -ENOMEM;
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goto out;
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}
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chunk_array_user = (uint64_t *)(unsigned long)(cs->in.chunks);
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if (copy_from_user(chunk_array, chunk_array_user,
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sizeof(uint64_t)*cs->in.num_chunks)) {
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r = -EFAULT;
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goto out;
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}
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p->nchunks = cs->in.num_chunks;
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p->chunks = kcalloc(p->nchunks, sizeof(struct amdgpu_cs_chunk),
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GFP_KERNEL);
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if (p->chunks == NULL) {
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r = -ENOMEM;
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goto out;
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}
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for (i = 0; i < p->nchunks; i++) {
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struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
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struct drm_amdgpu_cs_chunk user_chunk;
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uint32_t __user *cdata;
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chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
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if (copy_from_user(&user_chunk, chunk_ptr,
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sizeof(struct drm_amdgpu_cs_chunk))) {
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r = -EFAULT;
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goto out;
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}
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p->chunks[i].chunk_id = user_chunk.chunk_id;
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p->chunks[i].length_dw = user_chunk.length_dw;
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size = p->chunks[i].length_dw;
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cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
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p->chunks[i].user_ptr = cdata;
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p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
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if (p->chunks[i].kdata == NULL) {
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r = -ENOMEM;
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goto out;
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}
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size *= sizeof(uint32_t);
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if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
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r = -EFAULT;
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goto out;
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}
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switch (p->chunks[i].chunk_id) {
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case AMDGPU_CHUNK_ID_IB:
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p->num_ibs++;
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break;
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case AMDGPU_CHUNK_ID_FENCE:
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size = sizeof(struct drm_amdgpu_cs_chunk_fence);
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if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
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uint32_t handle;
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struct drm_gem_object *gobj;
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struct drm_amdgpu_cs_chunk_fence *fence_data;
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fence_data = (void *)p->chunks[i].kdata;
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handle = fence_data->handle;
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gobj = drm_gem_object_lookup(p->adev->ddev,
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p->filp, handle);
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if (gobj == NULL) {
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r = -EINVAL;
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goto out;
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}
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p->uf.bo = gem_to_amdgpu_bo(gobj);
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p->uf.offset = fence_data->offset;
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} else {
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r = -EINVAL;
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goto out;
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}
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break;
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case AMDGPU_CHUNK_ID_DEPENDENCIES:
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break;
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default:
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r = -EINVAL;
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goto out;
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}
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}
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p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
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if (!p->ibs) {
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r = -ENOMEM;
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goto out;
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}
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out:
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kfree(chunk_array);
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return r;
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}
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/* Returns how many bytes TTM can move per IB.
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*/
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static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
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{
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u64 real_vram_size = adev->mc.real_vram_size;
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u64 vram_usage = atomic64_read(&adev->vram_usage);
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/* This function is based on the current VRAM usage.
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*
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* - If all of VRAM is free, allow relocating the number of bytes that
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* is equal to 1/4 of the size of VRAM for this IB.
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* - If more than one half of VRAM is occupied, only allow relocating
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* 1 MB of data for this IB.
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*
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* - From 0 to one half of used VRAM, the threshold decreases
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* linearly.
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* __________________
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* 1/4 of -|\ |
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* VRAM | \ |
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* | \ |
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* | \ |
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* | \ |
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* | \ |
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* | \ |
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* | \________|1 MB
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* |----------------|
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* VRAM 0 % 100 %
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* used used
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*
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* Note: It's a threshold, not a limit. The threshold must be crossed
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* for buffer relocations to stop, so any buffer of an arbitrary size
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* can be moved as long as the threshold isn't crossed before
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* the relocation takes place. We don't want to disable buffer
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* relocations completely.
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*
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* The idea is that buffers should be placed in VRAM at creation time
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* and TTM should only do a minimum number of relocations during
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* command submission. In practice, you need to submit at least
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* a dozen IBs to move all buffers to VRAM if they are in GTT.
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*
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* Also, things can get pretty crazy under memory pressure and actual
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* VRAM usage can change a lot, so playing safe even at 50% does
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* consistently increase performance.
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*/
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u64 half_vram = real_vram_size >> 1;
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u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
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u64 bytes_moved_threshold = half_free_vram >> 1;
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return max(bytes_moved_threshold, 1024*1024ull);
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}
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int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
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{
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struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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struct amdgpu_device *adev = p->adev;
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struct amdgpu_bo_list_entry *lobj;
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struct list_head duplicates;
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struct amdgpu_bo *bo;
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u64 bytes_moved = 0, initial_bytes_moved;
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u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
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int r;
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INIT_LIST_HEAD(&duplicates);
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r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
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if (unlikely(r != 0)) {
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return r;
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}
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list_for_each_entry(lobj, &p->validated, tv.head) {
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bo = lobj->robj;
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if (!bo->pin_count) {
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u32 domain = lobj->prefered_domains;
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u32 current_domain =
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amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
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/* Check if this buffer will be moved and don't move it
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* if we have moved too many buffers for this IB already.
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*
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* Note that this allows moving at least one buffer of
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* any size, because it doesn't take the current "bo"
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* into account. We don't want to disallow buffer moves
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* completely.
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*/
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if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
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(domain & current_domain) == 0 && /* will be moved */
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bytes_moved > bytes_moved_threshold) {
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/* don't move it */
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domain = current_domain;
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}
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retry:
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amdgpu_ttm_placement_from_domain(bo, domain);
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initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
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r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
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bytes_moved += atomic64_read(&adev->num_bytes_moved) -
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initial_bytes_moved;
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if (unlikely(r)) {
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if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
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domain = lobj->allowed_domains;
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goto retry;
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}
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ttm_eu_backoff_reservation(&p->ticket, &p->validated);
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return r;
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}
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}
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lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
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}
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return 0;
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}
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static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
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{
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struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
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struct amdgpu_cs_buckets buckets;
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bool need_mmap_lock = false;
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int i, r;
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if (p->bo_list) {
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need_mmap_lock = p->bo_list->has_userptr;
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amdgpu_cs_buckets_init(&buckets);
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for (i = 0; i < p->bo_list->num_entries; i++)
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amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
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p->bo_list->array[i].priority);
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amdgpu_cs_buckets_get_list(&buckets, &p->validated);
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}
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p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
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&p->validated);
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if (need_mmap_lock)
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down_read(¤t->mm->mmap_sem);
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r = amdgpu_cs_list_validate(p);
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if (need_mmap_lock)
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up_read(¤t->mm->mmap_sem);
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return r;
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}
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static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
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{
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struct amdgpu_bo_list_entry *e;
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int r;
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list_for_each_entry(e, &p->validated, tv.head) {
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struct reservation_object *resv = e->robj->tbo.resv;
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r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
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if (r)
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return r;
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}
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return 0;
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}
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static int cmp_size_smaller_first(void *priv, struct list_head *a,
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struct list_head *b)
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{
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struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
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struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
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/* Sort A before B if A is smaller. */
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return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
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}
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/**
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* cs_parser_fini() - clean parser states
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* @parser: parser structure holding parsing context.
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* @error: error number
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*
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* If error is set than unvalidate buffer, otherwise just free memory
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* used by parsing context.
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**/
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static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
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{
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unsigned i;
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if (!error) {
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/* Sort the buffer list from the smallest to largest buffer,
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* which affects the order of buffers in the LRU list.
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* This assures that the smallest buffers are added first
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* to the LRU list, so they are likely to be later evicted
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* first, instead of large buffers whose eviction is more
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* expensive.
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*
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* This slightly lowers the number of bytes moved by TTM
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* per frame under memory pressure.
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*/
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list_sort(NULL, &parser->validated, cmp_size_smaller_first);
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ttm_eu_fence_buffer_objects(&parser->ticket,
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&parser->validated,
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&parser->ibs[parser->num_ibs-1].fence->base);
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} else if (backoff) {
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ttm_eu_backoff_reservation(&parser->ticket,
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&parser->validated);
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}
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if (parser->ctx)
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amdgpu_ctx_put(parser->ctx);
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if (parser->bo_list)
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amdgpu_bo_list_put(parser->bo_list);
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drm_free_large(parser->vm_bos);
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for (i = 0; i < parser->nchunks; i++)
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drm_free_large(parser->chunks[i].kdata);
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kfree(parser->chunks);
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if (parser->ibs)
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for (i = 0; i < parser->num_ibs; i++)
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amdgpu_ib_free(parser->adev, &parser->ibs[i]);
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kfree(parser->ibs);
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if (parser->uf.bo)
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drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
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}
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static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
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struct amdgpu_vm *vm)
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{
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struct amdgpu_device *adev = p->adev;
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struct amdgpu_bo_va *bo_va;
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struct amdgpu_bo *bo;
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int i, r;
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r = amdgpu_vm_update_page_directory(adev, vm);
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if (r)
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return r;
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r = amdgpu_vm_clear_freed(adev, vm);
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|
if (r)
|
|
return r;
|
|
|
|
if (p->bo_list) {
|
|
for (i = 0; i < p->bo_list->num_entries; i++) {
|
|
/* ignore duplicates */
|
|
bo = p->bo_list->array[i].robj;
|
|
if (!bo)
|
|
continue;
|
|
|
|
bo_va = p->bo_list->array[i].bo_va;
|
|
if (bo_va == NULL)
|
|
continue;
|
|
|
|
r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
|
|
if (r)
|
|
return r;
|
|
|
|
amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
|
|
}
|
|
}
|
|
|
|
return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
|
|
}
|
|
|
|
static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
|
|
struct amdgpu_cs_parser *parser)
|
|
{
|
|
struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
|
|
struct amdgpu_vm *vm = &fpriv->vm;
|
|
struct amdgpu_ring *ring;
|
|
int i, r;
|
|
|
|
if (parser->num_ibs == 0)
|
|
return 0;
|
|
|
|
/* Only for UVD/VCE VM emulation */
|
|
for (i = 0; i < parser->num_ibs; i++) {
|
|
ring = parser->ibs[i].ring;
|
|
if (ring->funcs->parse_cs) {
|
|
r = amdgpu_ring_parse_cs(ring, parser, i);
|
|
if (r)
|
|
return r;
|
|
}
|
|
}
|
|
|
|
mutex_lock(&vm->mutex);
|
|
r = amdgpu_bo_vm_update_pte(parser, vm);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
amdgpu_cs_sync_rings(parser);
|
|
|
|
r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
|
|
parser->filp);
|
|
|
|
out:
|
|
mutex_unlock(&vm->mutex);
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
|
|
{
|
|
if (r == -EDEADLK) {
|
|
r = amdgpu_gpu_reset(adev);
|
|
if (!r)
|
|
r = -EAGAIN;
|
|
}
|
|
return r;
|
|
}
|
|
|
|
static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
|
|
struct amdgpu_cs_parser *parser)
|
|
{
|
|
struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
|
|
struct amdgpu_vm *vm = &fpriv->vm;
|
|
int i, j;
|
|
int r;
|
|
|
|
for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
|
|
struct amdgpu_cs_chunk *chunk;
|
|
struct amdgpu_ib *ib;
|
|
struct drm_amdgpu_cs_chunk_ib *chunk_ib;
|
|
struct amdgpu_ring *ring;
|
|
|
|
chunk = &parser->chunks[i];
|
|
ib = &parser->ibs[j];
|
|
chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
|
|
|
|
if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
|
|
continue;
|
|
|
|
r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
|
|
chunk_ib->ip_instance, chunk_ib->ring,
|
|
&ring);
|
|
if (r)
|
|
return r;
|
|
|
|
if (ring->funcs->parse_cs) {
|
|
struct amdgpu_bo_va_mapping *m;
|
|
struct amdgpu_bo *aobj = NULL;
|
|
uint64_t offset;
|
|
uint8_t *kptr;
|
|
|
|
m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
|
|
&aobj);
|
|
if (!aobj) {
|
|
DRM_ERROR("IB va_start is invalid\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
|
|
(m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
|
|
DRM_ERROR("IB va_start+ib_bytes is invalid\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* the IB should be reserved at this point */
|
|
r = amdgpu_bo_kmap(aobj, (void **)&kptr);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
|
|
kptr += chunk_ib->va_start - offset;
|
|
|
|
r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
|
|
if (r) {
|
|
DRM_ERROR("Failed to get ib !\n");
|
|
return r;
|
|
}
|
|
|
|
memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
|
|
amdgpu_bo_kunmap(aobj);
|
|
} else {
|
|
r = amdgpu_ib_get(ring, vm, 0, ib);
|
|
if (r) {
|
|
DRM_ERROR("Failed to get ib !\n");
|
|
return r;
|
|
}
|
|
|
|
ib->gpu_addr = chunk_ib->va_start;
|
|
}
|
|
|
|
ib->length_dw = chunk_ib->ib_bytes / 4;
|
|
ib->flags = chunk_ib->flags;
|
|
ib->ctx = parser->ctx;
|
|
j++;
|
|
}
|
|
|
|
if (!parser->num_ibs)
|
|
return 0;
|
|
|
|
/* add GDS resources to first IB */
|
|
if (parser->bo_list) {
|
|
struct amdgpu_bo *gds = parser->bo_list->gds_obj;
|
|
struct amdgpu_bo *gws = parser->bo_list->gws_obj;
|
|
struct amdgpu_bo *oa = parser->bo_list->oa_obj;
|
|
struct amdgpu_ib *ib = &parser->ibs[0];
|
|
|
|
if (gds) {
|
|
ib->gds_base = amdgpu_bo_gpu_offset(gds);
|
|
ib->gds_size = amdgpu_bo_size(gds);
|
|
}
|
|
if (gws) {
|
|
ib->gws_base = amdgpu_bo_gpu_offset(gws);
|
|
ib->gws_size = amdgpu_bo_size(gws);
|
|
}
|
|
if (oa) {
|
|
ib->oa_base = amdgpu_bo_gpu_offset(oa);
|
|
ib->oa_size = amdgpu_bo_size(oa);
|
|
}
|
|
}
|
|
|
|
/* wrap the last IB with user fence */
|
|
if (parser->uf.bo) {
|
|
struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
|
|
|
|
/* UVD & VCE fw doesn't support user fences */
|
|
if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
|
|
ib->ring->type == AMDGPU_RING_TYPE_VCE)
|
|
return -EINVAL;
|
|
|
|
ib->user = &parser->uf;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
|
|
struct amdgpu_cs_parser *p)
|
|
{
|
|
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
|
|
struct amdgpu_ib *ib;
|
|
int i, j, r;
|
|
|
|
if (!p->num_ibs)
|
|
return 0;
|
|
|
|
/* Add dependencies to first IB */
|
|
ib = &p->ibs[0];
|
|
for (i = 0; i < p->nchunks; ++i) {
|
|
struct drm_amdgpu_cs_chunk_dep *deps;
|
|
struct amdgpu_cs_chunk *chunk;
|
|
unsigned num_deps;
|
|
|
|
chunk = &p->chunks[i];
|
|
|
|
if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
|
|
continue;
|
|
|
|
deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
|
|
num_deps = chunk->length_dw * 4 /
|
|
sizeof(struct drm_amdgpu_cs_chunk_dep);
|
|
|
|
for (j = 0; j < num_deps; ++j) {
|
|
struct amdgpu_fence *fence;
|
|
struct amdgpu_ring *ring;
|
|
struct amdgpu_ctx *ctx;
|
|
|
|
r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
|
|
deps[j].ip_instance,
|
|
deps[j].ring, &ring);
|
|
if (r)
|
|
return r;
|
|
|
|
ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
|
|
if (ctx == NULL)
|
|
return -EINVAL;
|
|
|
|
r = amdgpu_fence_recreate(ring, p->filp,
|
|
deps[j].handle,
|
|
&fence);
|
|
if (r) {
|
|
amdgpu_ctx_put(ctx);
|
|
return r;
|
|
}
|
|
|
|
amdgpu_sync_fence(&ib->sync, fence);
|
|
amdgpu_fence_unref(&fence);
|
|
amdgpu_ctx_put(ctx);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
union drm_amdgpu_cs *cs = data;
|
|
struct amdgpu_cs_parser parser;
|
|
int r, i;
|
|
bool reserved_buffers = false;
|
|
|
|
down_read(&adev->exclusive_lock);
|
|
if (!adev->accel_working) {
|
|
up_read(&adev->exclusive_lock);
|
|
return -EBUSY;
|
|
}
|
|
/* initialize parser */
|
|
memset(&parser, 0, sizeof(struct amdgpu_cs_parser));
|
|
parser.filp = filp;
|
|
parser.adev = adev;
|
|
r = amdgpu_cs_parser_init(&parser, data);
|
|
if (r) {
|
|
DRM_ERROR("Failed to initialize parser !\n");
|
|
amdgpu_cs_parser_fini(&parser, r, false);
|
|
up_read(&adev->exclusive_lock);
|
|
r = amdgpu_cs_handle_lockup(adev, r);
|
|
return r;
|
|
}
|
|
|
|
r = amdgpu_cs_parser_relocs(&parser);
|
|
if (r) {
|
|
if (r != -ERESTARTSYS) {
|
|
if (r == -ENOMEM)
|
|
DRM_ERROR("Not enough memory for command submission!\n");
|
|
else
|
|
DRM_ERROR("Failed to process the buffer list %d!\n", r);
|
|
}
|
|
}
|
|
|
|
if (!r) {
|
|
reserved_buffers = true;
|
|
r = amdgpu_cs_ib_fill(adev, &parser);
|
|
}
|
|
|
|
if (!r)
|
|
r = amdgpu_cs_dependencies(adev, &parser);
|
|
|
|
if (r) {
|
|
amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
|
|
up_read(&adev->exclusive_lock);
|
|
r = amdgpu_cs_handle_lockup(adev, r);
|
|
return r;
|
|
}
|
|
|
|
for (i = 0; i < parser.num_ibs; i++)
|
|
trace_amdgpu_cs(&parser, i);
|
|
|
|
r = amdgpu_cs_ib_vm_chunk(adev, &parser);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
|
|
cs->out.handle = parser.ibs[parser.num_ibs - 1].fence->seq;
|
|
out:
|
|
amdgpu_cs_parser_fini(&parser, r, true);
|
|
up_read(&adev->exclusive_lock);
|
|
r = amdgpu_cs_handle_lockup(adev, r);
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_cs_wait_ioctl - wait for a command submission to finish
|
|
*
|
|
* @dev: drm device
|
|
* @data: data from userspace
|
|
* @filp: file private
|
|
*
|
|
* Wait for the command submission identified by handle to finish.
|
|
*/
|
|
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp)
|
|
{
|
|
union drm_amdgpu_wait_cs *wait = data;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
|
|
struct amdgpu_fence *fence = NULL;
|
|
struct amdgpu_ring *ring = NULL;
|
|
struct amdgpu_ctx *ctx;
|
|
long r;
|
|
|
|
ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
|
|
if (ctx == NULL)
|
|
return -EINVAL;
|
|
|
|
r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
|
|
wait->in.ring, &ring);
|
|
if (r) {
|
|
amdgpu_ctx_put(ctx);
|
|
return r;
|
|
}
|
|
|
|
r = amdgpu_fence_recreate(ring, filp, wait->in.handle, &fence);
|
|
if (r) {
|
|
amdgpu_ctx_put(ctx);
|
|
return r;
|
|
}
|
|
|
|
r = fence_wait_timeout(&fence->base, true, timeout);
|
|
amdgpu_fence_unref(&fence);
|
|
amdgpu_ctx_put(ctx);
|
|
if (r < 0)
|
|
return r;
|
|
|
|
memset(wait, 0, sizeof(*wait));
|
|
wait->out.status = (r == 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_cs_find_bo_va - find bo_va for VM address
|
|
*
|
|
* @parser: command submission parser context
|
|
* @addr: VM address
|
|
* @bo: resulting BO of the mapping found
|
|
*
|
|
* Search the buffer objects in the command submission context for a certain
|
|
* virtual memory address. Returns allocation structure when found, NULL
|
|
* otherwise.
|
|
*/
|
|
struct amdgpu_bo_va_mapping *
|
|
amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
|
|
uint64_t addr, struct amdgpu_bo **bo)
|
|
{
|
|
struct amdgpu_bo_list_entry *reloc;
|
|
struct amdgpu_bo_va_mapping *mapping;
|
|
|
|
addr /= AMDGPU_GPU_PAGE_SIZE;
|
|
|
|
list_for_each_entry(reloc, &parser->validated, tv.head) {
|
|
if (!reloc->bo_va)
|
|
continue;
|
|
|
|
list_for_each_entry(mapping, &reloc->bo_va->mappings, list) {
|
|
if (mapping->it.start > addr ||
|
|
addr > mapping->it.last)
|
|
continue;
|
|
|
|
*bo = reloc->bo_va->bo;
|
|
return mapping;
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|