![Marek Olšák](/assets/img/avatar_default.png)
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
194 lines
4.9 KiB
C
194 lines
4.9 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: monk liu <monk.liu@amd.com>
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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static void amdgpu_ctx_do_release(struct kref *ref)
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{
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struct amdgpu_ctx *ctx;
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struct amdgpu_ctx_mgr *mgr;
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ctx = container_of(ref, struct amdgpu_ctx, refcount);
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mgr = &ctx->fpriv->ctx_mgr;
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idr_remove(&mgr->ctx_handles, ctx->id);
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kfree(ctx);
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}
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int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t *id, uint32_t flags)
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{
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int r;
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struct amdgpu_ctx *ctx;
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struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
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ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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mutex_lock(&mgr->lock);
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r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL);
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if (r < 0) {
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mutex_unlock(&mgr->lock);
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kfree(ctx);
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return r;
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}
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*id = (uint32_t)r;
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memset(ctx, 0, sizeof(*ctx));
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ctx->id = *id;
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ctx->fpriv = fpriv;
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kref_init(&ctx->refcount);
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mutex_unlock(&mgr->lock);
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return 0;
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}
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int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id)
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{
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struct amdgpu_ctx *ctx;
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struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
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mutex_lock(&mgr->lock);
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ctx = idr_find(&mgr->ctx_handles, id);
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if (ctx) {
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kref_put(&ctx->refcount, amdgpu_ctx_do_release);
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mutex_unlock(&mgr->lock);
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return 0;
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}
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mutex_unlock(&mgr->lock);
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return -EINVAL;
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}
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static int amdgpu_ctx_query(struct amdgpu_device *adev,
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struct amdgpu_fpriv *fpriv, uint32_t id,
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union drm_amdgpu_ctx_out *out)
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{
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struct amdgpu_ctx *ctx;
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struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
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unsigned reset_counter;
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mutex_lock(&mgr->lock);
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ctx = idr_find(&mgr->ctx_handles, id);
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if (!ctx) {
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mutex_unlock(&mgr->lock);
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return -EINVAL;
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}
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/* TODO: these two are always zero */
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out->state.flags = ctx->state.flags;
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out->state.hangs = ctx->state.hangs;
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/* determine if a GPU reset has occured since the last call */
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reset_counter = atomic_read(&adev->gpu_reset_counter);
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/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
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if (ctx->reset_counter == reset_counter)
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out->state.reset_status = AMDGPU_CTX_NO_RESET;
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else
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out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
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ctx->reset_counter = reset_counter;
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mutex_unlock(&mgr->lock);
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return 0;
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}
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void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
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{
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struct idr *idp;
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struct amdgpu_ctx *ctx;
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uint32_t id;
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struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
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idp = &mgr->ctx_handles;
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idr_for_each_entry(idp,ctx,id) {
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if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
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DRM_ERROR("ctx (id=%ul) is still alive\n",ctx->id);
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}
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mutex_destroy(&mgr->lock);
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}
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int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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int r;
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uint32_t id;
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uint32_t flags;
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union drm_amdgpu_ctx *args = data;
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_fpriv *fpriv = filp->driver_priv;
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r = 0;
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id = args->in.ctx_id;
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flags = args->in.flags;
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switch (args->in.op) {
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case AMDGPU_CTX_OP_ALLOC_CTX:
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r = amdgpu_ctx_alloc(adev, fpriv, &id, flags);
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args->out.alloc.ctx_id = id;
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break;
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case AMDGPU_CTX_OP_FREE_CTX:
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r = amdgpu_ctx_free(adev, fpriv, id);
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break;
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case AMDGPU_CTX_OP_QUERY_STATE:
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r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
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break;
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default:
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return -EINVAL;
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}
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return r;
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}
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struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
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{
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struct amdgpu_ctx *ctx;
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struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
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mutex_lock(&mgr->lock);
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ctx = idr_find(&mgr->ctx_handles, id);
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if (ctx)
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kref_get(&ctx->refcount);
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mutex_unlock(&mgr->lock);
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return ctx;
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}
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int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
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{
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struct amdgpu_fpriv *fpriv;
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struct amdgpu_ctx_mgr *mgr;
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if (ctx == NULL)
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return -EINVAL;
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fpriv = ctx->fpriv;
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mgr = &fpriv->ctx_mgr;
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mutex_lock(&mgr->lock);
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kref_put(&ctx->refcount, amdgpu_ctx_do_release);
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mutex_unlock(&mgr->lock);
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return 0;
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}
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