![Oded Gabbay](/assets/img/avatar_default.png)
This patch adds an interface file between amdgpu and amdkfd. This interface file is H/W agnostic, thus containing functions that operate the same for any AMD APU/GPU H/W generation. The functions in this interface mirror (some) of the functions in radeon_kfd.c (the radeon<-->amdkfd interface file). The main functions are: - amdgpu_amdkfd_init - initialize the amdkfd module - amdgpu_amdkfd_load_interface - load the H/W interface according to the currently probed device - amdgpu_amdkfd_device_probe - probe the device in amdkfd - amdgpu_amdkfd_device_init - initialize the device in amdkfd - amdgpu_amdkfd_interrupt - call the ISR of amdkfd - amdgpu_amdkfd_suspend - suspend callback from amdgpu - amdgpu_amdkfd_resume - resume callback from amdgpu This patch also modifies the relevant amdgpu files, to use this new interface. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
224 lines
6.3 KiB
C
224 lines
6.3 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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#include "amdgpu_amdkfd.h"
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/**
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* amdgpu_ih_ring_alloc - allocate memory for the IH ring
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate a ring buffer for the interrupt controller.
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* Returns 0 for success, errors for failure.
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*/
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static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
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{
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int r;
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/* Allocate ring buffer */
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if (adev->irq.ih.ring_obj == NULL) {
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r = amdgpu_bo_create(adev, adev->irq.ih.ring_size,
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PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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NULL, &adev->irq.ih.ring_obj);
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if (r) {
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DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
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return r;
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}
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r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_pin(adev->irq.ih.ring_obj,
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->irq.ih.gpu_addr);
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if (r) {
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amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
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DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r);
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return r;
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}
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r = amdgpu_bo_kmap(adev->irq.ih.ring_obj,
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(void **)&adev->irq.ih.ring);
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amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
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if (r) {
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DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r);
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return r;
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}
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}
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return 0;
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}
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/**
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* amdgpu_ih_ring_init - initialize the IH state
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*
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* @adev: amdgpu_device pointer
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*
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* Initializes the IH state and allocates a buffer
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* for the IH ring buffer.
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* Returns 0 for success, errors for failure.
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*/
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int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
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bool use_bus_addr)
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{
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u32 rb_bufsz;
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int r;
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/* Align ring size */
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rb_bufsz = order_base_2(ring_size / 4);
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ring_size = (1 << rb_bufsz) * 4;
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adev->irq.ih.ring_size = ring_size;
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adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
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adev->irq.ih.rptr = 0;
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adev->irq.ih.use_bus_addr = use_bus_addr;
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if (adev->irq.ih.use_bus_addr) {
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if (!adev->irq.ih.ring) {
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/* add 8 bytes for the rptr/wptr shadows and
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* add them to the end of the ring allocation.
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*/
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adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
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if (adev->irq.ih.ring == NULL)
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return -ENOMEM;
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adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
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(void *)adev->irq.ih.ring,
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adev->irq.ih.ring_size,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(adev->pdev, adev->irq.ih.rb_dma_addr)) {
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dev_err(&adev->pdev->dev, "Failed to DMA MAP the IH RB page\n");
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kfree((void *)adev->irq.ih.ring);
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return -ENOMEM;
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}
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adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
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adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
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}
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return 0;
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} else {
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r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
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if (r) {
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amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
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dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
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return r;
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}
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return amdgpu_ih_ring_alloc(adev);
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}
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}
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/**
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* amdgpu_ih_ring_fini - tear down the IH state
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*
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* @adev: amdgpu_device pointer
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*
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* Tears down the IH state and frees buffer
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* used for the IH ring buffer.
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*/
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void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
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{
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int r;
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if (adev->irq.ih.use_bus_addr) {
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if (adev->irq.ih.ring) {
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/* add 8 bytes for the rptr/wptr shadows and
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* add them to the end of the ring allocation.
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*/
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pci_unmap_single(adev->pdev, adev->irq.ih.rb_dma_addr,
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adev->irq.ih.ring_size + 8, PCI_DMA_BIDIRECTIONAL);
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kfree((void *)adev->irq.ih.ring);
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adev->irq.ih.ring = NULL;
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}
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} else {
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if (adev->irq.ih.ring_obj) {
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r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
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if (likely(r == 0)) {
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amdgpu_bo_kunmap(adev->irq.ih.ring_obj);
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amdgpu_bo_unpin(adev->irq.ih.ring_obj);
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amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
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}
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amdgpu_bo_unref(&adev->irq.ih.ring_obj);
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adev->irq.ih.ring = NULL;
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adev->irq.ih.ring_obj = NULL;
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}
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amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
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amdgpu_wb_free(adev, adev->irq.ih.rptr_offs);
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}
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}
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/**
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* amdgpu_ih_process - interrupt handler
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*
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* @adev: amdgpu_device pointer
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*
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* Interrupt hander (VI), walk the IH ring.
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* Returns irq process return code.
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*/
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int amdgpu_ih_process(struct amdgpu_device *adev)
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{
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struct amdgpu_iv_entry entry;
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u32 wptr;
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if (!adev->irq.ih.enabled || adev->shutdown)
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return IRQ_NONE;
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wptr = amdgpu_ih_get_wptr(adev);
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restart_ih:
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/* is somebody else already processing irqs? */
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if (atomic_xchg(&adev->irq.ih.lock, 1))
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return IRQ_NONE;
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DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
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/* Order reading of wptr vs. reading of IH ring data */
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rmb();
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while (adev->irq.ih.rptr != wptr) {
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u32 ring_index = adev->irq.ih.rptr >> 2;
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/* Before dispatching irq to IP blocks, send it to amdkfd */
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amdgpu_amdkfd_interrupt(adev,
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(const void *) &adev->irq.ih.ring[ring_index]);
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amdgpu_ih_decode_iv(adev, &entry);
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adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
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amdgpu_irq_dispatch(adev, &entry);
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}
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amdgpu_ih_set_rptr(adev);
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atomic_set(&adev->irq.ih.lock, 0);
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/* make sure wptr hasn't changed while processing */
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wptr = amdgpu_ih_get_wptr(adev);
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if (wptr != adev->irq.ih.rptr)
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goto restart_ih;
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return IRQ_HANDLED;
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}
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