![Christian König](/assets/img/avatar_default.png)
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
985 lines
23 KiB
C
985 lines
23 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Christian König <deathsimple@vodafone.de>
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "amdgpu.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_uvd.h"
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#include "cikd.h"
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#include "uvd/uvd_4_2_d.h"
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/* 1 second timeout */
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#define UVD_IDLE_TIMEOUT_MS 1000
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/* Firmware Names */
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#ifdef CONFIG_DRM_AMDGPU_CIK
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#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
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#define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
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#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
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#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
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#define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
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#endif
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#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
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#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
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/**
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* amdgpu_uvd_cs_ctx - Command submission parser context
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*
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* Used for emulating virtual memory support on UVD 4.2.
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*/
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struct amdgpu_uvd_cs_ctx {
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struct amdgpu_cs_parser *parser;
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unsigned reg, count;
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unsigned data0, data1;
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unsigned idx;
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unsigned ib_idx;
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/* does the IB has a msg command */
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bool has_msg_cmd;
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/* minimum buffer sizes */
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unsigned *buf_sizes;
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};
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#ifdef CONFIG_DRM_AMDGPU_CIK
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MODULE_FIRMWARE(FIRMWARE_BONAIRE);
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MODULE_FIRMWARE(FIRMWARE_KABINI);
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MODULE_FIRMWARE(FIRMWARE_KAVERI);
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MODULE_FIRMWARE(FIRMWARE_HAWAII);
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MODULE_FIRMWARE(FIRMWARE_MULLINS);
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#endif
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MODULE_FIRMWARE(FIRMWARE_TONGA);
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MODULE_FIRMWARE(FIRMWARE_CARRIZO);
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static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
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static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
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int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
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{
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unsigned long bo_size;
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const char *fw_name;
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const struct common_firmware_header *hdr;
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unsigned version_major, version_minor, family_id;
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int i, r;
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INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
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switch (adev->asic_type) {
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_BONAIRE:
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fw_name = FIRMWARE_BONAIRE;
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break;
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case CHIP_KABINI:
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fw_name = FIRMWARE_KABINI;
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break;
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case CHIP_KAVERI:
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fw_name = FIRMWARE_KAVERI;
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break;
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case CHIP_HAWAII:
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fw_name = FIRMWARE_HAWAII;
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break;
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case CHIP_MULLINS:
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fw_name = FIRMWARE_MULLINS;
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break;
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#endif
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case CHIP_TONGA:
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fw_name = FIRMWARE_TONGA;
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break;
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case CHIP_CARRIZO:
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fw_name = FIRMWARE_CARRIZO;
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break;
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default:
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return -EINVAL;
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}
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r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
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if (r) {
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dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
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fw_name);
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return r;
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}
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r = amdgpu_ucode_validate(adev->uvd.fw);
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if (r) {
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dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->uvd.fw);
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adev->uvd.fw = NULL;
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return r;
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}
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hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
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family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
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version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
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version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
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DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
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version_major, version_minor, family_id);
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bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
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+ AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
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r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
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return r;
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}
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r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
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if (r) {
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amdgpu_bo_unref(&adev->uvd.vcpu_bo);
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dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
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return r;
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}
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r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
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&adev->uvd.gpu_addr);
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if (r) {
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amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
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amdgpu_bo_unref(&adev->uvd.vcpu_bo);
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dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
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return r;
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}
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r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
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if (r) {
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dev_err(adev->dev, "(%d) UVD map failed\n", r);
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return r;
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}
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amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
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for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
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atomic_set(&adev->uvd.handles[i], 0);
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adev->uvd.filp[i] = NULL;
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}
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/* from uvd v5.0 HW addressing capacity increased to 64 bits */
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if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
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adev->uvd.address_64_bit = true;
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return 0;
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}
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int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
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{
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int r;
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if (adev->uvd.vcpu_bo == NULL)
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return 0;
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r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
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if (!r) {
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amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
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amdgpu_bo_unpin(adev->uvd.vcpu_bo);
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amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
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}
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amdgpu_bo_unref(&adev->uvd.vcpu_bo);
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amdgpu_ring_fini(&adev->uvd.ring);
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release_firmware(adev->uvd.fw);
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return 0;
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}
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int amdgpu_uvd_suspend(struct amdgpu_device *adev)
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{
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unsigned size;
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void *ptr;
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const struct common_firmware_header *hdr;
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int i;
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if (adev->uvd.vcpu_bo == NULL)
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return 0;
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for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
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if (atomic_read(&adev->uvd.handles[i]))
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break;
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if (i == AMDGPU_MAX_UVD_HANDLES)
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return 0;
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hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
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size = amdgpu_bo_size(adev->uvd.vcpu_bo);
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size -= le32_to_cpu(hdr->ucode_size_bytes);
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ptr = adev->uvd.cpu_addr;
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ptr += le32_to_cpu(hdr->ucode_size_bytes);
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adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
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memcpy(adev->uvd.saved_bo, ptr, size);
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return 0;
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}
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int amdgpu_uvd_resume(struct amdgpu_device *adev)
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{
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unsigned size;
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void *ptr;
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const struct common_firmware_header *hdr;
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unsigned offset;
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if (adev->uvd.vcpu_bo == NULL)
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return -EINVAL;
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hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
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offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
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memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
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(adev->uvd.fw->size) - offset);
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size = amdgpu_bo_size(adev->uvd.vcpu_bo);
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size -= le32_to_cpu(hdr->ucode_size_bytes);
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ptr = adev->uvd.cpu_addr;
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ptr += le32_to_cpu(hdr->ucode_size_bytes);
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if (adev->uvd.saved_bo != NULL) {
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memcpy(ptr, adev->uvd.saved_bo, size);
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kfree(adev->uvd.saved_bo);
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adev->uvd.saved_bo = NULL;
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} else
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memset(ptr, 0, size);
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return 0;
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}
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void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
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{
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struct amdgpu_ring *ring = &adev->uvd.ring;
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int i, r;
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for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
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uint32_t handle = atomic_read(&adev->uvd.handles[i]);
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if (handle != 0 && adev->uvd.filp[i] == filp) {
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struct amdgpu_fence *fence;
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amdgpu_uvd_note_usage(adev);
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r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
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if (r) {
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DRM_ERROR("Error destroying UVD (%d)!\n", r);
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continue;
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}
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amdgpu_fence_wait(fence, false);
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amdgpu_fence_unref(&fence);
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adev->uvd.filp[i] = NULL;
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atomic_set(&adev->uvd.handles[i], 0);
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}
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}
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}
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static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
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{
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int i;
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for (i = 0; i < rbo->placement.num_placement; ++i) {
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rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
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rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
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}
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}
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/**
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* amdgpu_uvd_cs_pass1 - first parsing round
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*
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* @ctx: UVD parser context
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*
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* Make sure UVD message and feedback buffers are in VRAM and
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* nobody is violating an 256MB boundary.
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*/
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static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
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{
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struct amdgpu_bo_va_mapping *mapping;
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struct amdgpu_bo *bo;
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uint32_t cmd, lo, hi;
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uint64_t addr;
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int r = 0;
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lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
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hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
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addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
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mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
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if (mapping == NULL) {
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DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
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return -EINVAL;
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}
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if (!ctx->parser->adev->uvd.address_64_bit) {
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/* check if it's a message or feedback command */
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cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
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if (cmd == 0x0 || cmd == 0x3) {
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/* yes, force it into VRAM */
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uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
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amdgpu_ttm_placement_from_domain(bo, domain);
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}
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amdgpu_uvd_force_into_uvd_segment(bo);
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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}
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return r;
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}
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/**
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* amdgpu_uvd_cs_msg_decode - handle UVD decode message
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*
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* @msg: pointer to message structure
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* @buf_sizes: returned buffer sizes
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*
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* Peek into the decode message and calculate the necessary buffer sizes.
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*/
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static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
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{
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unsigned stream_type = msg[4];
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unsigned width = msg[6];
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unsigned height = msg[7];
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unsigned dpb_size = msg[9];
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unsigned pitch = msg[28];
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unsigned level = msg[57];
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unsigned width_in_mb = width / 16;
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unsigned height_in_mb = ALIGN(height / 16, 2);
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unsigned fs_in_mb = width_in_mb * height_in_mb;
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unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
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image_size = width * height;
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image_size += image_size / 2;
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image_size = ALIGN(image_size, 1024);
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switch (stream_type) {
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case 0: /* H264 */
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case 7: /* H264 Perf */
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switch(level) {
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case 30:
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num_dpb_buffer = 8100 / fs_in_mb;
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break;
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case 31:
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num_dpb_buffer = 18000 / fs_in_mb;
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break;
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case 32:
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num_dpb_buffer = 20480 / fs_in_mb;
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break;
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case 41:
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num_dpb_buffer = 32768 / fs_in_mb;
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break;
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case 42:
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num_dpb_buffer = 34816 / fs_in_mb;
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break;
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case 50:
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num_dpb_buffer = 110400 / fs_in_mb;
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break;
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case 51:
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num_dpb_buffer = 184320 / fs_in_mb;
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break;
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default:
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num_dpb_buffer = 184320 / fs_in_mb;
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break;
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}
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num_dpb_buffer++;
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if (num_dpb_buffer > 17)
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num_dpb_buffer = 17;
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/* reference picture buffer */
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min_dpb_size = image_size * num_dpb_buffer;
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/* macroblock context buffer */
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min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
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/* IT surface buffer */
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min_dpb_size += width_in_mb * height_in_mb * 32;
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break;
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case 1: /* VC1 */
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/* reference picture buffer */
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min_dpb_size = image_size * 3;
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/* CONTEXT_BUFFER */
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min_dpb_size += width_in_mb * height_in_mb * 128;
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/* IT surface buffer */
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min_dpb_size += width_in_mb * 64;
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/* DB surface buffer */
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min_dpb_size += width_in_mb * 128;
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/* BP */
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tmp = max(width_in_mb, height_in_mb);
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min_dpb_size += ALIGN(tmp * 7 * 16, 64);
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break;
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case 3: /* MPEG2 */
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/* reference picture buffer */
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min_dpb_size = image_size * 3;
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break;
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case 4: /* MPEG4 */
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/* reference picture buffer */
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min_dpb_size = image_size * 3;
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/* CM */
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min_dpb_size += width_in_mb * height_in_mb * 64;
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/* IT surface buffer */
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min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
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break;
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case 16: /* H265 */
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image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
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image_size = ALIGN(image_size, 256);
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num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
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min_dpb_size = image_size * num_dpb_buffer;
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break;
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default:
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DRM_ERROR("UVD codec not handled %d!\n", stream_type);
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return -EINVAL;
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}
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if (width > pitch) {
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DRM_ERROR("Invalid UVD decoding target pitch!\n");
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return -EINVAL;
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}
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if (dpb_size < min_dpb_size) {
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|
DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
|
|
dpb_size, min_dpb_size);
|
|
return -EINVAL;
|
|
}
|
|
|
|
buf_sizes[0x1] = dpb_size;
|
|
buf_sizes[0x2] = image_size;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_uvd_cs_msg - handle UVD message
|
|
*
|
|
* @ctx: UVD parser context
|
|
* @bo: buffer object containing the message
|
|
* @offset: offset into the buffer object
|
|
*
|
|
* Peek into the UVD message and extract the session id.
|
|
* Make sure that we don't open up to many sessions.
|
|
*/
|
|
static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
|
|
struct amdgpu_bo *bo, unsigned offset)
|
|
{
|
|
struct amdgpu_device *adev = ctx->parser->adev;
|
|
int32_t *msg, msg_type, handle;
|
|
struct fence *f;
|
|
void *ptr;
|
|
|
|
int i, r;
|
|
|
|
if (offset & 0x3F) {
|
|
DRM_ERROR("UVD messages must be 64 byte aligned!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
f = reservation_object_get_excl(bo->tbo.resv);
|
|
if (f) {
|
|
r = amdgpu_fence_wait((struct amdgpu_fence *)f, false);
|
|
if (r) {
|
|
DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
|
|
return r;
|
|
}
|
|
}
|
|
|
|
r = amdgpu_bo_kmap(bo, &ptr);
|
|
if (r) {
|
|
DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
|
|
return r;
|
|
}
|
|
|
|
msg = ptr + offset;
|
|
|
|
msg_type = msg[1];
|
|
handle = msg[2];
|
|
|
|
if (handle == 0) {
|
|
DRM_ERROR("Invalid UVD handle!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (msg_type == 1) {
|
|
/* it's a decode msg, calc buffer sizes */
|
|
r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
|
|
amdgpu_bo_kunmap(bo);
|
|
if (r)
|
|
return r;
|
|
|
|
} else if (msg_type == 2) {
|
|
/* it's a destroy msg, free the handle */
|
|
for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
|
|
atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
|
|
amdgpu_bo_kunmap(bo);
|
|
return 0;
|
|
} else {
|
|
/* it's a create msg */
|
|
amdgpu_bo_kunmap(bo);
|
|
|
|
if (msg_type != 0) {
|
|
DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* it's a create msg, no special handling needed */
|
|
}
|
|
|
|
/* create or decode, validate the handle */
|
|
for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
|
|
if (atomic_read(&adev->uvd.handles[i]) == handle)
|
|
return 0;
|
|
}
|
|
|
|
/* handle not found try to alloc a new one */
|
|
for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
|
|
if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
|
|
adev->uvd.filp[i] = ctx->parser->filp;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
DRM_ERROR("No more free UVD handles!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_uvd_cs_pass2 - second parsing round
|
|
*
|
|
* @ctx: UVD parser context
|
|
*
|
|
* Patch buffer addresses, make sure buffer sizes are correct.
|
|
*/
|
|
static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
|
|
{
|
|
struct amdgpu_bo_va_mapping *mapping;
|
|
struct amdgpu_bo *bo;
|
|
struct amdgpu_ib *ib;
|
|
uint32_t cmd, lo, hi;
|
|
uint64_t start, end;
|
|
uint64_t addr;
|
|
int r;
|
|
|
|
lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
|
|
hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
|
|
addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
|
|
|
|
mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
|
|
if (mapping == NULL)
|
|
return -EINVAL;
|
|
|
|
start = amdgpu_bo_gpu_offset(bo);
|
|
|
|
end = (mapping->it.last + 1 - mapping->it.start);
|
|
end = end * AMDGPU_GPU_PAGE_SIZE + start;
|
|
|
|
addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
|
|
start += addr;
|
|
|
|
ib = &ctx->parser->ibs[ctx->ib_idx];
|
|
ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
|
|
ib->ptr[ctx->data1] = start >> 32;
|
|
|
|
cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
|
|
if (cmd < 0x4) {
|
|
if ((end - start) < ctx->buf_sizes[cmd]) {
|
|
DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
|
|
(unsigned)(end - start),
|
|
ctx->buf_sizes[cmd]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
} else if ((cmd != 0x100) && (cmd != 0x204)) {
|
|
DRM_ERROR("invalid UVD command %X!\n", cmd);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!ctx->parser->adev->uvd.address_64_bit) {
|
|
if ((start >> 28) != ((end - 1) >> 28)) {
|
|
DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
|
|
start, end);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((cmd == 0 || cmd == 0x3) &&
|
|
(start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
|
|
DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
|
|
start, end);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
if (cmd == 0) {
|
|
ctx->has_msg_cmd = true;
|
|
r = amdgpu_uvd_cs_msg(ctx, bo, addr);
|
|
if (r)
|
|
return r;
|
|
} else if (!ctx->has_msg_cmd) {
|
|
DRM_ERROR("Message needed before other commands are send!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_uvd_cs_reg - parse register writes
|
|
*
|
|
* @ctx: UVD parser context
|
|
* @cb: callback function
|
|
*
|
|
* Parse the register writes, call cb on each complete command.
|
|
*/
|
|
static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
|
|
int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
|
|
{
|
|
struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
|
|
int i, r;
|
|
|
|
ctx->idx++;
|
|
for (i = 0; i <= ctx->count; ++i) {
|
|
unsigned reg = ctx->reg + i;
|
|
|
|
if (ctx->idx >= ib->length_dw) {
|
|
DRM_ERROR("Register command after end of CS!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (reg) {
|
|
case mmUVD_GPCOM_VCPU_DATA0:
|
|
ctx->data0 = ctx->idx;
|
|
break;
|
|
case mmUVD_GPCOM_VCPU_DATA1:
|
|
ctx->data1 = ctx->idx;
|
|
break;
|
|
case mmUVD_GPCOM_VCPU_CMD:
|
|
r = cb(ctx);
|
|
if (r)
|
|
return r;
|
|
break;
|
|
case mmUVD_ENGINE_CNTL:
|
|
break;
|
|
default:
|
|
DRM_ERROR("Invalid reg 0x%X!\n", reg);
|
|
return -EINVAL;
|
|
}
|
|
ctx->idx++;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_uvd_cs_packets - parse UVD packets
|
|
*
|
|
* @ctx: UVD parser context
|
|
* @cb: callback function
|
|
*
|
|
* Parse the command stream packets.
|
|
*/
|
|
static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
|
|
int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
|
|
{
|
|
struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
|
|
int r;
|
|
|
|
for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
|
|
uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
|
|
unsigned type = CP_PACKET_GET_TYPE(cmd);
|
|
switch (type) {
|
|
case PACKET_TYPE0:
|
|
ctx->reg = CP_PACKET0_GET_REG(cmd);
|
|
ctx->count = CP_PACKET_GET_COUNT(cmd);
|
|
r = amdgpu_uvd_cs_reg(ctx, cb);
|
|
if (r)
|
|
return r;
|
|
break;
|
|
case PACKET_TYPE2:
|
|
++ctx->idx;
|
|
break;
|
|
default:
|
|
DRM_ERROR("Unknown packet type %d !\n", type);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_uvd_ring_parse_cs - UVD command submission parser
|
|
*
|
|
* @parser: Command submission parser context
|
|
*
|
|
* Parse the command stream, patch in addresses as necessary.
|
|
*/
|
|
int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
|
|
{
|
|
struct amdgpu_uvd_cs_ctx ctx = {};
|
|
unsigned buf_sizes[] = {
|
|
[0x00000000] = 2048,
|
|
[0x00000001] = 32 * 1024 * 1024,
|
|
[0x00000002] = 2048 * 1152 * 3,
|
|
[0x00000003] = 2048,
|
|
};
|
|
struct amdgpu_ib *ib = &parser->ibs[ib_idx];
|
|
int r;
|
|
|
|
if (ib->length_dw % 16) {
|
|
DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
|
|
ib->length_dw);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ctx.parser = parser;
|
|
ctx.buf_sizes = buf_sizes;
|
|
ctx.ib_idx = ib_idx;
|
|
|
|
/* first round, make sure the buffers are actually in the UVD segment */
|
|
r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
|
|
if (r)
|
|
return r;
|
|
|
|
/* second round, patch buffer addresses into the command stream */
|
|
r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
|
|
if (r)
|
|
return r;
|
|
|
|
if (!ctx.has_msg_cmd) {
|
|
DRM_ERROR("UVD-IBs need a msg command!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
amdgpu_uvd_note_usage(ctx.parser->adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
|
|
struct amdgpu_bo *bo,
|
|
struct amdgpu_fence **fence)
|
|
{
|
|
struct ttm_validate_buffer tv;
|
|
struct ww_acquire_ctx ticket;
|
|
struct list_head head;
|
|
struct amdgpu_ib ib;
|
|
uint64_t addr;
|
|
int i, r;
|
|
|
|
memset(&tv, 0, sizeof(tv));
|
|
tv.bo = &bo->tbo;
|
|
|
|
INIT_LIST_HEAD(&head);
|
|
list_add(&tv.head, &head);
|
|
|
|
r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
|
|
if (r)
|
|
return r;
|
|
|
|
if (!bo->adev->uvd.address_64_bit) {
|
|
amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
|
|
amdgpu_uvd_force_into_uvd_segment(bo);
|
|
}
|
|
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
|
|
if (r)
|
|
goto err;
|
|
|
|
r = amdgpu_ib_get(ring, NULL, 64, &ib);
|
|
if (r)
|
|
goto err;
|
|
|
|
addr = amdgpu_bo_gpu_offset(bo);
|
|
ib.ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
|
|
ib.ptr[1] = addr;
|
|
ib.ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
|
|
ib.ptr[3] = addr >> 32;
|
|
ib.ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
|
|
ib.ptr[5] = 0;
|
|
for (i = 6; i < 16; ++i)
|
|
ib.ptr[i] = PACKET2(0);
|
|
ib.length_dw = 16;
|
|
|
|
r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
|
|
if (r)
|
|
goto err;
|
|
ttm_eu_fence_buffer_objects(&ticket, &head, &ib.fence->base);
|
|
|
|
if (fence)
|
|
*fence = amdgpu_fence_ref(ib.fence);
|
|
|
|
amdgpu_ib_free(ring->adev, &ib);
|
|
amdgpu_bo_unref(&bo);
|
|
return 0;
|
|
|
|
err:
|
|
ttm_eu_backoff_reservation(&ticket, &head);
|
|
return r;
|
|
}
|
|
|
|
/* multiple fence commands without any stream commands in between can
|
|
crash the vcpu so just try to emmit a dummy create/destroy msg to
|
|
avoid this */
|
|
int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
|
|
struct amdgpu_fence **fence)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
struct amdgpu_bo *bo;
|
|
uint32_t *msg;
|
|
int r, i;
|
|
|
|
r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
|
|
AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_bo_reserve(bo, false);
|
|
if (r) {
|
|
amdgpu_bo_unref(&bo);
|
|
return r;
|
|
}
|
|
|
|
r = amdgpu_bo_kmap(bo, (void **)&msg);
|
|
if (r) {
|
|
amdgpu_bo_unreserve(bo);
|
|
amdgpu_bo_unref(&bo);
|
|
return r;
|
|
}
|
|
|
|
/* stitch together an UVD create msg */
|
|
msg[0] = cpu_to_le32(0x00000de4);
|
|
msg[1] = cpu_to_le32(0x00000000);
|
|
msg[2] = cpu_to_le32(handle);
|
|
msg[3] = cpu_to_le32(0x00000000);
|
|
msg[4] = cpu_to_le32(0x00000000);
|
|
msg[5] = cpu_to_le32(0x00000000);
|
|
msg[6] = cpu_to_le32(0x00000000);
|
|
msg[7] = cpu_to_le32(0x00000780);
|
|
msg[8] = cpu_to_le32(0x00000440);
|
|
msg[9] = cpu_to_le32(0x00000000);
|
|
msg[10] = cpu_to_le32(0x01b37000);
|
|
for (i = 11; i < 1024; ++i)
|
|
msg[i] = cpu_to_le32(0x0);
|
|
|
|
amdgpu_bo_kunmap(bo);
|
|
amdgpu_bo_unreserve(bo);
|
|
|
|
return amdgpu_uvd_send_msg(ring, bo, fence);
|
|
}
|
|
|
|
int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
|
|
struct amdgpu_fence **fence)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
struct amdgpu_bo *bo;
|
|
uint32_t *msg;
|
|
int r, i;
|
|
|
|
r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
|
|
AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_bo_reserve(bo, false);
|
|
if (r) {
|
|
amdgpu_bo_unref(&bo);
|
|
return r;
|
|
}
|
|
|
|
r = amdgpu_bo_kmap(bo, (void **)&msg);
|
|
if (r) {
|
|
amdgpu_bo_unreserve(bo);
|
|
amdgpu_bo_unref(&bo);
|
|
return r;
|
|
}
|
|
|
|
/* stitch together an UVD destroy msg */
|
|
msg[0] = cpu_to_le32(0x00000de4);
|
|
msg[1] = cpu_to_le32(0x00000002);
|
|
msg[2] = cpu_to_le32(handle);
|
|
msg[3] = cpu_to_le32(0x00000000);
|
|
for (i = 4; i < 1024; ++i)
|
|
msg[i] = cpu_to_le32(0x0);
|
|
|
|
amdgpu_bo_kunmap(bo);
|
|
amdgpu_bo_unreserve(bo);
|
|
|
|
return amdgpu_uvd_send_msg(ring, bo, fence);
|
|
}
|
|
|
|
static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
|
|
{
|
|
struct amdgpu_device *adev =
|
|
container_of(work, struct amdgpu_device, uvd.idle_work.work);
|
|
unsigned i, fences, handles = 0;
|
|
|
|
fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
|
|
|
|
for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
|
|
if (atomic_read(&adev->uvd.handles[i]))
|
|
++handles;
|
|
|
|
if (fences == 0 && handles == 0) {
|
|
if (adev->pm.dpm_enabled) {
|
|
amdgpu_dpm_enable_uvd(adev, false);
|
|
} else {
|
|
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
|
|
}
|
|
} else {
|
|
schedule_delayed_work(&adev->uvd.idle_work,
|
|
msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
|
|
}
|
|
}
|
|
|
|
static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
|
|
{
|
|
bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
|
|
set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
|
|
msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
|
|
|
|
if (set_clocks) {
|
|
if (adev->pm.dpm_enabled) {
|
|
amdgpu_dpm_enable_uvd(adev, true);
|
|
} else {
|
|
amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
|
|
}
|
|
}
|
|
}
|